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| author | Simon Tatham <simon.tatham@arm.com> | 2020-02-17 17:05:26 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2020-02-18 09:34:50 +0000 |
| commit | b6236e94799e43fad1f024e84ed56a85d9a3623f (patch) | |
| tree | 920d814a429f965219758c14c55b34b095379974 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | c8b3196e54308b0113d2a0888d13ccc92e3b7ccc (diff) | |
[ARM,MVE] Add the vrev16q, vrev32q, vrev64q family.
Summary:
These intrinsics just reorder the lanes of a vector, so the natural IR
representation is as a shufflevector operation. Existing LLVM codegen
already recognizes those particular shufflevectors and generates the
MVE VREV instruction.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74334
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions