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| author | Simon Tatham <simon.tatham@arm.com> | 2020-02-17 17:05:39 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2020-02-18 09:34:50 +0000 |
| commit | 68b49f7ef49eec068b7ddcf86c868e2a193e64e1 (patch) | |
| tree | e4425d2d5509f57bb5fc0d313edaacff1916d414 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | b6236e94799e43fad1f024e84ed56a85d9a3623f (diff) | |
[ARM,MVE] Add intrinsics vclzq and vclsq.
Summary:
vclzq maps nicely to the existing target-independent @llvm.ctlz IR
intrinsic. But vclsq ('count leading sign bits') has no corresponding
target-independent intrinsic, so I've made up @llvm.arm.mve.vcls.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74335
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions