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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2020-04-21 10:44:46 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2020-04-30 10:18:40 +0000 |
| commit | 672b62ea21dfe5f9bfb2b0362785f2685be830a0 (patch) | |
| tree | 32e666900d279e8c948ee8019a45de55ff83d523 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 058cd8c5be1cb6c74c0cfc154a61ea859e1c8811 (diff) | |
[AArch64][SVE] Custom lowering of floating-point reductions
Summary:
This patch implements custom floating-point reduction ISD nodes that
have vector results, which are used to lower the following intrinsics:
* llvm.aarch64.sve.fadda
* llvm.aarch64.sve.faddv
* llvm.aarch64.sve.fmaxv
* llvm.aarch64.sve.fmaxnmv
* llvm.aarch64.sve.fminv
* llvm.aarch64.sve.fminnmv
SVE reduction instructions keep their result within a vector register,
with all other bits set to zero.
Changes in this patch were implemented by Paul Walker and Sander de
Smalen.
Reviewers: sdesmalen, efriedma, rengolin
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D78723
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions