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| author | Sander de Smalen <sander.desmalen@arm.com> | 2023-05-22 13:52:06 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2023-05-22 13:52:06 +0000 |
| commit | 437a516da8055c28c89dead53c012f71a4331eb9 (patch) | |
| tree | 28dd39712b4043b9f706e70ad72c6ea71d0f61da /lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp | |
| parent | 387c49f693c82bdf8b9b0f1ef48a92f51bb781b4 (diff) | |
[SME2/SVE2p1] Change psel intrinsic such that the result/first operand are not overloaded.
All the bits of the first operand are copied to the destination register,
if the tested bit (in the second source operand) is active. This means we
copy over all vscale x 16 x i1's of the first operand. There is no need to
overload that type.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D150958
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp')
0 files changed, 0 insertions, 0 deletions