diff options
| author | Sander de Smalen <sander.desmalen@arm.com> | 2023-05-22 13:37:34 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2023-05-22 13:51:02 +0000 |
| commit | 387c49f693c82bdf8b9b0f1ef48a92f51bb781b4 (patch) | |
| tree | de96b5ec25c0696497d58352d13bc899609757da /lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp | |
| parent | d33910a8cc838587886a7302e7f8e6761bb5a89c (diff) | |
[AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1
These intrinsics are used to implement multi-vector load/store intrinsics that loads
or stores a tuple of 2 or 4 values, based on a predicate-as-counter operand, e.g.
__attribute__((arm_streaming))
svuint8x2_t svld1[_u8]_x2(svcount_t png, const uint8_t *rn);
__attribute__((arm_streaming))
void svst1[_u8_x2](svcount_t png, uint8_t *rn, svuint8x2_t zt);
As described in https://github.com/ARM-software/acle/pull/217
Reviewed By: CarolineConcatto
Differential Revision: https://reviews.llvm.org/D150956
Diffstat (limited to 'lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp')
0 files changed, 0 insertions, 0 deletions