1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=CI %s
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: m0_gws_init0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX9-LABEL: name: m0_gws_init0
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: $m0 = S_MOV_B32 -1
; GFX9-NEXT: S_NOP 0
; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; VI-LABEL: name: m0_gws_init0
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: $m0 = S_MOV_B32 -1
; VI-NEXT: S_NOP 0
; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; CI-LABEL: name: m0_gws_init0
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: $m0 = S_MOV_B32 -1
; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; SI-LABEL: name: m0_gws_init0
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: $m0 = S_MOV_B32 -1
; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; GFX10-LABEL: name: m0_gws_init0
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: $m0 = S_MOV_B32 -1
; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
$m0 = S_MOV_B32 -1
DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
...
---
name: m0_gws_init1
tracksRegLiveness: true
body: |
bb.0:
; GFX9-LABEL: name: m0_gws_init1
; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; GFX9-NEXT: $m0 = S_MOV_B32 -1
; GFX9-NEXT: S_NOP 0
; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; VI-LABEL: name: m0_gws_init1
; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; VI-NEXT: $m0 = S_MOV_B32 -1
; VI-NEXT: S_NOP 0
; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; CI-LABEL: name: m0_gws_init1
; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; CI-NEXT: $m0 = S_MOV_B32 -1
; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; SI-LABEL: name: m0_gws_init1
; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; SI-NEXT: $m0 = S_MOV_B32 -1
; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; GFX10-LABEL: name: m0_gws_init1
; GFX10: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; GFX10-NEXT: $m0 = S_MOV_B32 -1
; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
$m0 = S_MOV_B32 -1
DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
...
# Test a typical situation where m0 needs to be set from a VGPR
# through readfirstlane
---
name: m0_gws_readlane
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX9-LABEL: name: m0_gws_readlane
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; GFX9-NEXT: $m0 = S_MOV_B32 $sgpr0
; GFX9-NEXT: S_NOP 0
; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; VI-LABEL: name: m0_gws_readlane
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; VI-NEXT: $m0 = S_MOV_B32 $sgpr0
; VI-NEXT: S_NOP 0
; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; CI-LABEL: name: m0_gws_readlane
; CI: liveins: $vgpr0, $vgpr1
; CI-NEXT: {{ $}}
; CI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; CI-NEXT: $m0 = S_MOV_B32 $sgpr0
; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; SI-LABEL: name: m0_gws_readlane
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; SI-NEXT: $m0 = S_MOV_B32 $sgpr0
; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
;
; GFX10-LABEL: name: m0_gws_readlane
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; GFX10-NEXT: $m0 = S_MOV_B32 $sgpr0
; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
$sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
$m0 = S_MOV_B32 $sgpr0
DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
...
|
