1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
|
#ifndef LLVM_TOOLS_LLVM_BOLT_SYS_AARCH64
#define LLVM_TOOLS_LLVM_BOLT_SYS_AARCH64
// Save all registers while keeping 16B stack alignment
#define SAVE_ALL \
"stp x0, x1, [sp, #-16]!\n" \
"stp x2, x3, [sp, #-16]!\n" \
"stp x4, x5, [sp, #-16]!\n" \
"stp x6, x7, [sp, #-16]!\n" \
"stp x8, x9, [sp, #-16]!\n" \
"stp x10, x11, [sp, #-16]!\n" \
"stp x12, x13, [sp, #-16]!\n" \
"stp x14, x15, [sp, #-16]!\n" \
"stp x16, x17, [sp, #-16]!\n" \
"stp x18, x19, [sp, #-16]!\n" \
"stp x20, x21, [sp, #-16]!\n" \
"stp x22, x23, [sp, #-16]!\n" \
"stp x24, x25, [sp, #-16]!\n" \
"stp x26, x27, [sp, #-16]!\n" \
"stp x28, x29, [sp, #-16]!\n" \
"str x30, [sp,#-16]!\n"
// Mirrors SAVE_ALL
#define RESTORE_ALL \
"ldr x30, [sp], #16\n" \
"ldp x28, x29, [sp], #16\n" \
"ldp x26, x27, [sp], #16\n" \
"ldp x24, x25, [sp], #16\n" \
"ldp x22, x23, [sp], #16\n" \
"ldp x20, x21, [sp], #16\n" \
"ldp x18, x19, [sp], #16\n" \
"ldp x16, x17, [sp], #16\n" \
"ldp x14, x15, [sp], #16\n" \
"ldp x12, x13, [sp], #16\n" \
"ldp x10, x11, [sp], #16\n" \
"ldp x8, x9, [sp], #16\n" \
"ldp x6, x7, [sp], #16\n" \
"ldp x4, x5, [sp], #16\n" \
"ldp x2, x3, [sp], #16\n" \
"ldp x0, x1, [sp], #16\n"
// Anonymous namespace covering everything but our library entry point
namespace {
// Get the difference between runtime address of .text section and
// static address in section header table. Can be extracted from arbitrary
// pc value recorded at runtime to get the corresponding static address, which
// in turn can be used to search for indirect call description. Needed because
// indirect call descriptions are read-only non-relocatable data.
uint64_t getTextBaseAddress() {
uint64_t DynAddr;
uint64_t StaticAddr;
__asm__ volatile("b .instr%=\n\t"
".StaticAddr%=:\n\t"
".dword __hot_end\n\t"
".instr%=:\n\t"
"ldr %0, .StaticAddr%=\n\t"
"adrp %1, __hot_end\n\t"
"add %1, %1, :lo12:__hot_end\n\t"
: "=r"(StaticAddr), "=r"(DynAddr));
return DynAddr - StaticAddr;
}
uint64_t __read(uint64_t fd, const void *buf, uint64_t count) {
uint64_t ret;
register uint64_t x0 __asm__("x0") = fd;
register const void *x1 __asm__("x1") = buf;
register uint64_t x2 __asm__("x2") = count;
register uint32_t w8 __asm__("w8") = 63;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __write(uint64_t fd, const void *buf, uint64_t count) {
uint64_t ret;
register uint64_t x0 __asm__("x0") = fd;
register const void *x1 __asm__("x1") = buf;
register uint64_t x2 __asm__("x2") = count;
register uint32_t w8 __asm__("w8") = 64;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
void *__mmap(uint64_t addr, uint64_t size, uint64_t prot, uint64_t flags,
uint64_t fd, uint64_t offset) {
void *ret;
register uint64_t x0 __asm__("x0") = addr;
register uint64_t x1 __asm__("x1") = size;
register uint64_t x2 __asm__("x2") = prot;
register uint64_t x3 __asm__("x3") = flags;
register uint64_t x4 __asm__("x4") = fd;
register uint64_t x5 __asm__("x5") = offset;
register uint32_t w8 __asm__("w8") = 222;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(x4), "r"(x5), "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __munmap(void *addr, uint64_t size) {
uint64_t ret;
register void *x0 __asm__("x0") = addr;
register uint64_t x1 __asm__("x1") = size;
register uint32_t w8 __asm__("w8") = 215;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __exit(uint64_t code) {
uint64_t ret;
register uint64_t x0 __asm__("x0") = code;
register uint32_t w8 __asm__("w8") = 94;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0)
: "r"(w8)
: "cc", "memory", "x1");
return ret;
}
uint64_t __open(const char *pathname, uint64_t flags, uint64_t mode) {
uint64_t ret;
register int x0 __asm__("x0") = -100;
register const char *x1 __asm__("x1") = pathname;
register uint64_t x2 __asm__("x2") = flags;
register uint64_t x3 __asm__("x3") = mode;
register uint32_t w8 __asm__("w8") = 56;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(w8)
: "cc", "memory");
return ret;
}
long __getdents64(unsigned int fd, dirent64 *dirp, size_t count) {
long ret;
register unsigned int x0 __asm__("x0") = fd;
register dirent64 *x1 __asm__("x1") = dirp;
register size_t x2 __asm__("x2") = count;
register uint32_t w8 __asm__("w8") = 61;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __readlink(const char *pathname, char *buf, size_t bufsize) {
uint64_t ret;
register int x0 __asm__("x0") = -100;
register const char *x1 __asm__("x1") = pathname;
register char *x2 __asm__("x2") = buf;
register size_t x3 __asm__("x3") = bufsize;
register uint32_t w8 __asm__("w8") = 78; // readlinkat
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __lseek(uint64_t fd, uint64_t pos, uint64_t whence) {
uint64_t ret;
register uint64_t x0 __asm__("x0") = fd;
register uint64_t x1 __asm__("x1") = pos;
register uint64_t x2 __asm__("x2") = whence;
register uint32_t w8 __asm__("w8") = 62;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
int __ftruncate(uint64_t fd, uint64_t length) {
int ret;
register uint64_t x0 __asm__("x0") = fd;
register uint64_t x1 __asm__("x1") = length;
register uint32_t w8 __asm__("w8") = 46;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(w8)
: "cc", "memory");
return ret;
}
int __close(uint64_t fd) {
int ret;
register uint64_t x0 __asm__("x0") = fd;
register uint32_t w8 __asm__("w8") = 57;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0)
: "r"(w8)
: "cc", "memory", "x1");
return ret;
}
int __madvise(void *addr, size_t length, int advice) {
int ret;
register void *x0 __asm__("x0") = addr;
register size_t x1 __asm__("x1") = length;
register int x2 __asm__("x2") = advice;
register uint32_t w8 __asm__("w8") = 233;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
int __uname(struct UtsNameTy *buf) {
int ret;
register UtsNameTy *x0 __asm__("x0") = buf;
register uint32_t w8 __asm__("w8") = 160;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0)
: "r"(w8)
: "cc", "memory", "x1");
return ret;
}
uint64_t __nanosleep(const timespec *req, timespec *rem) {
uint64_t ret;
register const timespec *x0 __asm__("x0") = req;
register timespec *x1 __asm__("x1") = rem;
register uint32_t w8 __asm__("w8") = 101;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(w8)
: "cc", "memory");
return ret;
}
int64_t __fork() {
uint64_t ret;
// clone instead of fork with flags
// "CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD"
register uint64_t x0 __asm__("x0") = 0x1200011;
register uint64_t x1 __asm__("x1") = 0;
register uint64_t x2 __asm__("x2") = 0;
register uint64_t x3 __asm__("x3") = 0;
register uint64_t x4 __asm__("x4") = 0;
register uint32_t w8 __asm__("w8") = 220;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(x4), "r"(w8)
: "cc", "memory");
return ret;
}
int __mprotect(void *addr, size_t len, int prot) {
int ret;
register void *x0 __asm__("x0") = addr;
register size_t x1 __asm__("x1") = len;
register int x2 __asm__("x2") = prot;
register uint32_t w8 __asm__("w8") = 226;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __getpid() {
uint64_t ret;
register uint32_t w8 __asm__("w8") = 172;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret)
: "r"(w8)
: "cc", "memory", "x0", "x1");
return ret;
}
uint64_t __getppid() {
uint64_t ret;
register uint32_t w8 __asm__("w8") = 173;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret)
: "r"(w8)
: "cc", "memory", "x0", "x1");
return ret;
}
int __setpgid(uint64_t pid, uint64_t pgid) {
int ret;
register uint64_t x0 __asm__("x0") = pid;
register uint64_t x1 __asm__("x1") = pgid;
register uint32_t w8 __asm__("w8") = 154;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(w8)
: "cc", "memory");
return ret;
}
uint64_t __getpgid(uint64_t pid) {
uint64_t ret;
register uint64_t x0 __asm__("x0") = pid;
register uint32_t w8 __asm__("w8") = 155;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0)
: "r"(w8)
: "cc", "memory", "x1");
return ret;
}
int __kill(uint64_t pid, int sig) {
int ret;
register uint64_t x0 __asm__("x0") = pid;
register int x1 __asm__("x1") = sig;
register uint32_t w8 __asm__("w8") = 129;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(w8)
: "cc", "memory");
return ret;
}
int __fsync(int fd) {
int ret;
register int x0 __asm__("x0") = fd;
register uint32_t w8 __asm__("w8") = 82;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0)
: "r"(w8)
: "cc", "memory", "x1");
return ret;
}
uint64_t __sigprocmask(int how, const void *set, void *oldset) {
uint64_t ret;
register int x0 __asm__("x0") = how;
register const void *x1 __asm__("x1") = set;
register void *x2 __asm__("x2") = oldset;
register long x3 asm("x3") = 8;
register uint32_t w8 __asm__("w8") = 135;
__asm__ __volatile__("svc #0\n"
"mov %0, x0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(w8)
: "cc", "memory");
return ret;
}
int __prctl(int option, unsigned long arg2, unsigned long arg3,
unsigned long arg4, unsigned long arg5) {
int ret;
register int x0 __asm__("x0") = option;
register unsigned long x1 __asm__("x1") = arg2;
register unsigned long x2 __asm__("x2") = arg3;
register unsigned long x3 __asm__("x3") = arg4;
register unsigned long x4 __asm__("x4") = arg5;
register uint32_t w8 __asm__("w8") = 167;
__asm__ __volatile__("svc #0\n"
"mov %w0, w0"
: "=r"(ret), "+r"(x0), "+r"(x1)
: "r"(x2), "r"(x3), "r"(x4), "r"(w8)
: "cc", "memory");
return ret;
}
} // anonymous namespace
#endif
|