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AgeCommit message (Expand)Author
2025-11-21[MLIR] [XeGPU] Fix dropSgLayoutAndData & dropInstData in SliceAttr (#168618)Nishant Patel
2025-11-21[mlir][presburger] Fix PresburgerSpace comment (#167292)lonely eagle
2025-11-21[acc][flang] Implement acc interface for tracking type descriptors (#168982)Razvan Lupusoru
2025-11-21[mlir][ROCDL] Adds wmma scaled intrinsics for gfx1250 (#165915)Muzammiluddin Syed
2025-11-21Revert "[MLIR][GPU] subgroup_mma fp64 extension" (#169049)Fabian Mora
2025-11-21[MLIR][GPU] subgroup_mma fp64 extension (#165873)Giacomo Castiglioni
2025-11-21[mlir][py][c] Enable setting block arg locations. (#169033)Jacques Pienaar
2025-11-21[MLIR][XeGPU][TransformOps] Add slice_dims argument to set_op_layout_attr and...Tuomas Kärnä
2025-11-21[mlir][llvm] Handle debug record import edge cases (#168774)Tobias Gysi
2025-11-21[mlir][linalg] Clean up op verifiers without custom checks(NFC) (#168712)Longsheng Mou
2025-11-20[mlir][SCF] Add `scf::tileAndFuseConsumer` that tiles a consumer into a given...MaheshRavishankar
2025-11-20[mlir] Replace `llvm::OwningArrayRef` with `std::vector` (#168803)David Stone
2025-11-20[mlir][spirv] Add support for SwitchOp (#168713)Igor Wodiany
2025-11-20Revert "[mlir][Pass] Fix crash when applying a pass to an optional interface"...Matthias Springer
2025-11-20[mlir][Pass] Fix crash when applying a pass to an optional interface (#168499)Matthias Springer
2025-11-19[MLIR][Vector] Add unroll pattern for vector.shape_cast (#167738)Nishant Patel
2025-11-19[MLIR][NVVM] Doc fixes (#168716)Guray Ozen
2025-11-19[mlir][LLVM] Resync memory effect attribute with LLVM IR (#168568)darkbuck
2025-11-19[MLIR][ODS] Fully qualify namespace for mlir::Attribute in ODS generated code...BogdanDragosV
2025-11-19Reland "[MLIR][NVVM] Add tcgen05.mma MLIR Ops (#164356)" (#168638)Pradeep Kumar
2025-11-19[mlir] Use dictionary order to order the pass decl (NFC) (#168648)lonely eagle
2025-11-18[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767)Jianhui Li
2025-11-18[OpenACC] add cl::values to ACCImplicitRoutineOptions (#168601)Scott Manley
2025-11-18[mlir][acc][flang] Introduce OpenACC interfaces for globals (#168614)Razvan Lupusoru
2025-11-18Revert "[MLIR][NVVM] Add tcgen05.mma MLIR Ops" (#168583)Mehdi Amini
2025-11-18[mlir][tosa] Add a pass to narrow i64 to i32 (#165581)Luke Hutton
2025-11-18[MLIR][NVVM] Move the docs to markdown file (#168375)Guray Ozen
2025-11-18[MLIR][NVVM] Add tcgen05.mma MLIR Ops (#164356)Pradeep Kumar
2025-11-18[mlir][SCF] Add pass option to deactivate pattern rollback (#168481)Matthias Springer
2025-11-18[mlir][NVVM] Add no-rollback option to NVVM lowering passes (#168477)Matthias Springer
2025-11-17[mlir][acc] Add ACCImplicitRoutine pass for implicit `acc routine` (#168433)Razvan Lupusoru
2025-11-17[mlir][XeGPU] Use DistributeLayoutAttr instead of LayoutAttr for load gather/...Dmitry Chigarev
2025-11-17Fix side effects for LLVM integer operations (udiv, sdiv) incorrectly marked ...Jeremy Furtek
2025-11-17Add 'exact' flag to arith.shrui/shrsi/divsi/divui operations (#165923)Jeremy Furtek
2025-11-17[MLIR][SparseTensor] Dense Outer Loop Ordering Strategy (#160168)Govind Malasani
2025-11-17[MLIR][NVVM][Docs] Explain memory spaces (#168059)Guray Ozen
2025-11-17[MLIR][NVVM][NFC] Re-order mem_scope and shared_space attrs (#168348)Durgadoss R
2025-11-17[MLIR] Add verification that symbol operations must not have results (#168390)Tim Noack
2025-11-17[mlir][amdgpu] Fix documentation and verifiers (#167369)Erick Ochoa Lopez
2025-11-17[MLIR][NVVM] Add support for shared::cta destination (#168056)Durgadoss R
2025-11-15[mlir][MemRef] Add UB as a dependent dialect and use `ub.poison` for Mem2Reg ...Fabian Mora
2025-11-14[mlir][acc] Check legality of symbols in acc regions (#167957)Razvan Lupusoru
2025-11-14[MLIR] Extend vector.scatter to accept tensor as base (#165548)Ryutaro Okada
2025-11-14[MLIR][LLVM] Debug info: import debug records directly (#167812)Bruno Cardoso Lopes
2025-11-14[mlir][tosa] Allow int64 index tensors in gather/scatter (#167894)Luke Hutton
2025-11-14[Linalg] Add basic infra to add matchers for linalg.*conv*/*pool* ops (#163724)Abhishek Varma
2025-11-13[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where p...Muzammiluddin Syed
2025-11-13[mlir][NVVM] Make sure barrier reduction attr can roundtrip (#167958)Valentin Clement (バレンタイン クレメン)
2025-11-13[ROCDL] Added missing cluster.ids op (gfx1250) (#167890)Ravil Dorozhinskii
2025-11-13[MLIR][LLVMIR] Add {s,u}cmp intrinsics to LLVM dialect (#167870)Robert Konicar
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