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path: root/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
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2025-11-21DAG: Handle poison in m_Undef (#168288)Matt Arsenault
2025-10-29[DAG] Add generic m_TernaryOp() / m_c_TernaryOp() matchers (#165520)陈子昂
Similar to the m_BinOp/m_c_BinOp matchers, this patch introduces generic matchers for SelectionDAG nodes with three operands. This includes: - Adding m_TernaryOp() and m_c_TernaryOp() templates in SDPatternMatch.h. - Adding comprehensive test coverage in SelectionDAGPatternMatchTest.cpp. Fixes #165378
2025-10-22[DAG] Create SDPatternMatch method `m_SelectLike` to match `ISD::Select` and ↵kper
`ISD::VSelect` (#164069) Fixes #150019
2025-08-01Add m_SelectCCLike matcher to match SELECT_CC or SELECT with SETCC (#149646)黃國庭
Fix #147282 and Follow-up to #148834 --------- Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
2025-07-30[LLVM][SelectionDAG] Align poison/undef binop folds with IR. (#149334)Paul Walker
The "at construction" binop folds in SelectionDAG::getNode() has different behaviour when compared to the equivalent LLVM IR. This PR makes the behaviour consistent while also extending the coverage to include signed/unsigned max/min operations.
2025-07-09[AMDGPU] SelectionDAG divergence tracking should take into account Target ↵alex-t
divergency. (#147560) This is the next attempt to upstream this: https://github.com/llvm/llvm-project/pull/144947 The las one caused build errors in AArch64. Issue was resolved.
2025-07-08[DAG] SDPatternMatch - add matching for SELECT_CC patterns to min/max like ↵Simon Pilgrim
matchers (#147071) Fixes #147083
2025-07-07[NFC] Remove redundant namespace qualifier in SelectionDAGPatternMatchTest ↵woruyu
(#147443) ### Summary This PR remove the extra llvm::SDPatternMatch prefix in https://github.com/llvm/llvm-project/pull/147044
2025-07-07[DAG] SDPatternMatch m_Zero/m_One/m_AllOnes have inconsistent undef h… ↵woruyu
(#147044) ### Summary This PR resolves https://github.com/llvm/llvm-project/issues/146871 This PR resolves https://github.com/llvm/llvm-project/issues/140745 Refactor m_Zero/m_One/m_AllOnes all use struct template function to match and AllowUndefs=false as default.
2025-07-03Revert "[AMDGPU] SelectionDAG divergence tracking should take into account ↵Florian Hahn
Target divergency. (#144947)" This reverts commit 8ac7210b7f0ad49ae7809bf6a9faf2f7433384b0. This breaks the building the AArch64 backend, e.g. see https://github.com/llvm/llvm-project/pull/144947 Revert to unbreak the build. Also reverts follow-up commits 1e76f012db3ccfaa05e238812e572b5b6d12c17e.
2025-07-03[AMDGPU] SelectionDAG divergence tracking should take into account Target ↵alex-t
divergency. (#144947) If a kernel is known to be executing only a single lane, IR UniformityAnalysis will take note of that (via GCNTTIImpl::hasBranchDivergence) and report that all values are uniform. SelectionDAG's built-in divergence tracking should do the same.
2025-06-30[DAG] Implement SDPatternMatch `m_SpecificScalarVT` and ↵zhaohui
`m_SpecificVectorElementVT` matchers (#144996) Resolves https://github.com/llvm/llvm-project/issues/144477 --------- Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
2025-06-26[DAG] Add `SDPatternMatch::m_Load` (#145481)Abhishek Kaushik
Add SDPatternMatch matcher and unit test coverage for `ISD::LOAD` opcode. This only matches the loaded value i.e. ResNo 0 and not the output chain. e.g. ``` m_Load(m_Value(), m_Value(), m_Value()) ``` The first value is the input chain, the second is the base pointer, and the last value is the offset.
2025-06-26[DAG] Add SDPatternMatch::m_Result to match a specific SDValue result (#145775)Min-Yih Hsu
`m_Result<N>` matches a SDValue that is the N-th result of the defining SDNode. This is useful for creating a more fine-grained matching on SDNode with multiple results. ----- Inspired by #145481
2025-06-20[SDPatternMatch] Add m_Poison matcher (#144860)Ming Yan
Add SDPatternMatch matcher and unit test coverage for ISD::POISON opcode e.g. ``` m_InsertElt(m_Poison(), m_Value(), m_Zero()) ```
2025-06-18[DAG] Implement SDPatternMatch `m_Abs()` matcher (#144512)Rajveer Singh Bharadwaj
2025-06-08[llvm] Compare std::optional<T> to values directly (NFC) (#143340)Kazu Hirata
This patch transforms: X && *X == Y to: X == Y where X is of std::optional<T>, and Y is of T or similar.
2025-05-06[DAG] Add SDPatternMatch::m_BitwiseLogic common matcher for AND/OR/XOR nodes ↵Simon Pilgrim
(#138301)
2025-03-21[DAG] SDPatternMatch - add matchers for reassociatable binops (#119985)Ethan Kaji
fixes https://github.com/llvm/llvm-project/issues/118847 implements matchers for reassociatable opcodes as well as helpers for commonly used reassociatable binary matchers. --------- Co-authored-by: Min-Yih Hsu <min@myhsu.dev>
2025-03-12[TargetRegistry] Accept Triple in createTargetMachine() (NFC) (#130940)Nikita Popov
This avoids doing a Triple -> std::string -> Triple round trip in lots of places, now that the Module stores a Triple.
2025-01-17[DAG] Add SDPatternMatch::m_BitCast matcher (#123327)Simon Pilgrim
Simplifies a future patch
2025-01-11[SDPatternMatch] Add Matcher m_Undef (#122521)Amr Hesham
Add Matcher `m_Undef` Fixes: #122439
2025-01-09[SDPatternMatch] Add matchers m_ExtractSubvector and m_InsertSubvector (#120212)Thor Preimesberger
Fixes #118846
2025-01-06Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (#119592)Aidan Goldfarb
This PR resolves #118845. I aimed to mirror the implementation `m_Shuffle()` in [PatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/PatternMatch.h). Updated [SDPatternMatch.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/CodeGen/SDPatternMatch.h) - Added `struct m_Mask` to match masks (`ArrayRef<int>`) - Added two `m_Shuffle` functions. One to match independently of mask, and one to match considering mask. - Added `struct SDShuffle_match` to match `ISD::VECTOR_SHUFFLE` considering mask Updated [SDPatternMatchTest.cpp](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp) - Added `matchVecShuffle` test, which tests the behavior of both `m_Shuffle()` functions - - - I am not sure if my test coverage is complete. I am not sure how to test a `false` match, simply test against a different instruction? [Other tests ](https://github.com/llvm/llvm-project/blob/main/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp#L175), such as for `VSelect`, test against `Select`. I am not sure if there is an analogous instruction to compare against for `VECTOR_SHUFFLE`. I would appreciate some pointers in this area. In general, please liberally critique this PR! --------- Co-authored-by: Aidan <aidan.goldfarb@mail.mcgill.ca>
2024-12-13[DAG] SDPatternMatch - Add m_ExtractElt and m_InsertElt matchers (#119430)Chris White
Resolves #118844
2024-11-14Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)Matin Raayai
Following discussions in #110443, and the following earlier discussions in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html, https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine` interface classes. More specifically: 1. Makes `TargetMachine` the only class implemented under `TargetMachine.h` in the `Target` library. 2. `TargetMachine` contains target-specific interface functions that relate to IR/CodeGen/MC constructs, whereas before (at least on paper) it was supposed to have only IR/MC constructs. Any Target that doesn't want to use the independent code generator simply does not implement them, and returns either `false` or `nullptr`. 3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming aims to make the purpose of `LLVMTargetMachine` clearer. Its interface was moved under the CodeGen library, to further emphasis its usage in Targets that use CodeGen directly. 4. Makes `TargetMachine` the only interface used across LLVM and its projects. With these changes, `CodeGenCommonTMImpl` is simply a set of shared function implementations of `TargetMachine`, and CodeGen users don't need to static cast to `LLVMTargetMachine` every time they need a CodeGen-specific feature of the `TargetMachine`. 5. More importantly, does not change any requirements regarding library linking. cc @arsenm @aeubanks
2024-10-31[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)Yingwei Zheng
This patch allows using enumeration values directly and simplifies the implementation with bitwise logic. It addresses the comment in https://github.com/llvm/llvm-project/pull/113808#discussion_r1819923625.
2024-10-16[DAG] SDPatternMatch - add missing ROTL/ROTR matchersSimon Pilgrim
2024-10-16[DAG] SDPatternMatch - add missing BSWAP/CTPOP/CTTZ matchersSimon Pilgrim
2024-10-15Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum ↵c8ef
patterns in addition to the existing ISD nodes." (#112203) This patch adds icmp+select patterns for integer min/max matchers in SDPatternMatch, similar to those in IR PatternMatch. Reapply #111774. Closes #108218.
2024-10-14Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum ↵c8ef
patterns in addition to the existing ISD nodes." (#112200) Reverts llvm/llvm-project#111774 This appears to be causing some tests to fail.
2024-10-14[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns ↵c8ef
in addition to the existing ISD nodes. (#111774) Closes #108218. This patch adds icmp+select patterns for integer min/max matchers in SDPatternMatch, similar to those in IR PatternMatch.
2024-09-15[DAGCombine] Count leading ones: refine post DAG/Type Legalisation if ↵Robert Dazi
promotion (#102877) This PR is related to #99591. In this PR, instead of modifying how the legalisation occurs depending on surrounding instructions, we refine after legalisation. This PR has two parts: * `SDPatternMatch/MatchContext`: Modify a little bit the code to match Operands (used by `m_Node(...)`) and Unary/Binary/Ternary Patterns to make it compatible with `VPMatchContext`, instead of only `m_Opc` supported. Some tests were added to ensure no regressions. * `DAGCombiner`: Add a `foldSubCtlzNot` which detect and rewrite the patterns using matching context. Remaining Tasks: - [ ] GlobalISel - [ ] Currently the pattern matching will occur even before legalisation. Should I restrict it to specific stages instead ? - [ ] Style: Add a visitVP_SUB ?? Move `foldSubCtlzNot` in another location for style consistency purpose ? @topperc --------- Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
2024-08-18[DAG][PatternMatch] Add support for matchers with flags; NFCNoah Goldstein
Add support for matching with `SDNodeFlags` i.e `add` with `nuw`. This patch adds helpers for `or disjoint` or `zext nneg` with the same names as we have in IR/PatternMatch api. Closes #103060
2024-08-16[DAG] SD Pattern Match: Operands patterns with VP Context (#103308)v01dXYZ
Currently, when using a VP match context with `sd_context_match`, only Opcode matching is possible (`m_Opc(Opcode)`). This PR suggest a way to make patterns with Operands (eg `m_Node`, `m_Add`, ...) works with a VP context. This PR blocks another PR https://github.com/llvm/llvm-project/pull/102877. Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
2024-08-15[DAG] Adding m_FPToUI and m_FPToSI to SDPatternMatch.h (#104044)Jorge Botto
Adds m_FPToUI/m_FPToSI matchers for ISD::FP_TO_UINT/ISD::FP_TO_SINT in SDPatternMatch.h with suitable test coverage. Fixes https://github.com/llvm/llvm-project/issues/103872
2024-07-29[DAG] Add SDPatternMatch::m_VSelect (#100758)Michael Maitland
As per the comment in https://github.com/llvm/llvm-project/pull/100686#pullrequestreview-2201991135
2024-07-29[DAG] Add SDPatternMatch for VScale nodesMichael Maitland
2024-07-26 [DAG] Add SDPatternMatch::m_Select (#100686)Michael Maitland
This will enable us to use SDPatternMatch with ISD::SELECT SDNodes in the future.
2024-07-26CodeGen: Remove MachineModuleInfo reference from MachineFunction (#100357)Matt Arsenault
This avoids another unserializable field. Move the DbgInfoAvailable field into the AsmPrinter, which is only really a cache/convenience bit for checking a direct IR module metadata check.
2024-07-24Reland "SelectionDAG: Avoid using MachineFunction::getMMI" (#99779)Vitaly Buka
Reverts llvm/llvm-project#99777 Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>
2024-07-20Revert "SelectionDAG: Avoid using MachineFunction::getMMI" (#99777)Vitaly Buka
Reverts llvm/llvm-project#99696 https://lab.llvm.org/buildbot/#/builders/164/builds/1262
2024-07-20SelectionDAG: Avoid using MachineFunction::getMMI (#99696)Matt Arsenault
2024-07-14[DAG] Add SDPatternMatch::m_SetCC and update some combines to use it (#98646)Simon Pilgrim
The plan is to add more TernaryOp in the future (SELECT/VSELECT and FMA in particular)
2024-06-28[IR] Don't include Module.h in Analysis.h (NFC) (#97023)Nikita Popov
Replace it with a forward declaration instead. Analysis.h is pulled in by all passes, but not all passes need to access the module.
2024-06-14[SDPatternMatch] Only match ISD::SIGN_EXTEND in m_SExt (#95415)c8ef
Context: https://github.com/llvm/llvm-project/pull/95365#discussion_r1638236603 The current implementation of `m_SExt` matches both `ISD::SIGN_EXTEND` and `ISD::SIGN_EXTEND_INREG`. However, in cases where we specifically need to match _only_ `ISD::SIGN_EXTEND`, such as in the SelectionDAG graph below, this can lead to issues and unintended combinations. ``` SelectionDAG has 13 nodes: t0: ch,glue = EntryToken t2: v2i32,ch = CopyFromReg t0, Register:v2i32 %0 t21: v2i32 = sign_extend_inreg t2, ValueType:ch:v2i8 t4: v2i32,ch = CopyFromReg t0, Register:v2i32 %1 t22: v2i32 = sign_extend_inreg t4, ValueType:ch:v2i8 t23: v2i32 = avgfloors t21, t22 t24: v2i32 = sign_extend_inreg t23, ValueType:ch:v2i8 t15: ch,glue = CopyToReg t0, Register:v2i32 $d0, t24 t16: ch = AArch64ISD::RET_GLUE t15, Register:v2i32 $d0, t15:1 ```
2024-05-02[SDPatternMatch] Add m_CondCode, m_NoneOf, and some SExt improvements (#90762)Min-Yih Hsu
- Add m_CondCode to match the ISD::CondCode value from CondCodeSDNode - Add m_NoneOf combinator - m_SExt now recognizes sext_inreg
2024-03-20[DAG] Add SDPatternMatch ↵Marc Auberer
m_ZExtOrSelf/m_SExtOrSelf/m_AExtOrSelf/m_TruncOrSelf matchers (#85480) Fixes #85395
2024-03-18[SelectionDAG] Add m_Neg and m_Not pattern matcher and update DAGCombiner ↵zicwangupa
(#85365) Resolves #85065 --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2024-03-14[DAG] Add SDPatternMatch m_SMin/m_SMax/m_UMin/m_UMax matchersSimon Pilgrim
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-11 17:55:27 +0000