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AgeCommit message (Expand)Author
2025-11-21[RISCV] Update SpacemiT-X60 vector mask instructions latencies (#150644)Mikhail R. Gadelha
2025-11-21[IR2VEC] Rewrite triples.mir and entities.mir. NFC (#168574)David Green
2025-11-20[llvm][dsymutil][test] Create dedicated AArch64 directory (#168895)Michael Buch
2025-11-20[NFC] Reduce the size of test input in incompatible_dwarf_version.test (#168825)Jinjie Huang
2025-11-20[llvm-dwp] Give more information when incompatible version found (#168511)Jinjie Huang
2025-11-19[llvm][DebugInfo] Add support for _BitInt in DWARFTypePrinter (#168382)Michael Buch
2025-11-19[RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions...Mikhail R. Gadelha
2025-11-19[ObjectYAML][CodeView] Include inline annotation data (#168211)nerix
2025-11-19[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)Joshua Rodriguez
2025-11-19[AArch64] Update zero latency instructions in Neoverse scheduling tables (#16...Simon Wallis
2025-11-18Modify llvm-dwp to be able to emit string tables over 4GB without losing data...Greg Clayton
2025-11-15[llvm-pdbutil] Create DBI section headers in yaml2pdb (#166566)nerix
2025-11-14AMDGPU: Select vector reg class for divergent build_vector (#168169)Matt Arsenault
2025-11-13[AArch64] Add SchedReadAdvance to the Neoverse-N3 scheduling model (#167302)Asher Dobrescu
2025-11-13[opt] Add --save-stats option (#167304)Tomer Shafir
2025-11-13[AArch64] Fix SVE FADDP latency on Neoverse-N3 (#167676)Asher Dobrescu
2025-11-12[RISCV] Update SpacemiT-X60 vector permutation instructions latencies (#152738)Mikhail R. Gadelha
2025-11-11[llvm-offload-wrapper] Fix Triple and OpenMP handling (#167580)Joseph Huber
2025-11-11AMDGPU: Start using RegClassByHwMode for wavesize operandsMatt Arsenault
2025-11-10[llc] Fix save-stats test in read only directories (#167403)Michael Jones
2025-11-10[tools][llc] Make save-stats.ll test target independent (#167238)Tomer Shafir
2025-11-09[tools][llc] Fix save-stats.ll require aarch64 target (#167218)Tomer Shafir
2025-11-09[tools][llc] Add `--save-stats` option (#163967)Tomer Shafir
2025-11-08[llvm-rc] Don't interpret integer literals as octal numbers in rc.exe mode (#...Martin Storsjö
2025-11-07[fix test] Move typedefs-with-same-name.test into ARM folder (#167005)Roy Shi
2025-11-07[dsymutil] Fix parallel linker's self-recursive typedef DIE by including refe...Roy Shi
2025-11-07[CAS] Add llvm-cas tools to inspect on-disk LLVMCAS (#166481)Steven Wu
2025-11-06[DirectX] Remove llvm.assume intrinsic (#166697)Farzon Lotfi
2025-11-06[RISCV] Update SpacemiT-X60 vector reduction operations latencies (#152737)Mikhail R. Gadelha
2025-11-06[InstrProf] Fix frontend generated function hash (#165358)Stephen Senran Zhang
2025-11-06[IR] llvm.reloc.none intrinsic for no-op symbol references (#147427)Daniel Thornburgh
2025-11-06Reapply "[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_chec...Valery Pykhtin
2025-11-05Analysis: Add RuntimeLibcall analysis pass (#165196)Matt Arsenault
2025-11-05[TLI] Add basic support for nextafter/nexttoward libcalls (#166250)Sayan Sivakumaran
2025-11-05Revert "[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_check...Valery Pykhtin
2025-11-05[utils][UpdateLLCTestChecks] Add MIR support to update_llc_test_checks.py. (#...Valery Pykhtin
2025-11-04[IR] Add new function attribute nocreateundeforpoison (#164809)Jay Foad
2025-11-04[llvm][dwarfdump] Add --child-tags option to filter by DWARF tags (#165720)Michael Buch
2025-11-03[dsymutil] Add option to copy swiftmodules built from interface (#165293)Roy Shi
2025-11-01[llvm-config] Add new flag `--quote-paths` to optionally quote and escape pat...Alexandre Ganea
2025-11-01[UTC] CHECK-EMPTY instead of skipping blank lines (#165718)Kunqiu Chen
2025-10-31[X86] Remove AMX-TRANSPOSE (#165556)Mikołaj Piróg
2025-10-31[llvm][dwarfdump] Show name of referenced DW_TAG_APPLE_property (#165537)Michael Buch
2025-10-30[SHT_LLVM_BB_ADDR] Implement ELF and YAML support for Propeller CFG data in P...Rahman Lavaee
2025-10-29[DirectX] Use an allow-list of DXIL compatible module metadata (#165290)Finn Plummer
2025-10-28[UTC] Indent switch cases (#165212)Kunqiu Chen
2025-10-28[test][DebugInfo] Fix location of test build artifacts (#165349)Jordan Rupprecht
2025-10-28[AArch64] Initial sched model for Neoverse V3, V3AE (#163932)Simon Wallis
2025-10-27[DirectX] Allow llvm.assume intrinsic to pass on to DXIL (#165311)Farzon Lotfi
2025-10-28[DebugInfo] Support to get TU for hash from .debug_types.dwo section in DWARF...Liu Ke
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