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path: root/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
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2024-07-10[GISel] Make create.*InstructionSelector arguments const (#98243)Michael Maitland
The InstructionSelector objects all take these arguments in as `const`. This function does not modify the object. Therefore we can mark them as `const` here.
2024-03-17[CodeGen] Use LocationSize for MMO getSize (#84751)David Green
This is part of #70452 that changes the type used for the external interface of MMO to LocationSize as opposed to uint64_t. This means the constructors take LocationSize, and convert ~UINT64_C(0) to LocationSize::beforeOrAfter(). The getSize methods return a LocationSize. This allows us to be more precise with unknown sizes, not accidentally treating them as unsigned values, and in the future should allow us to add proper scalable vector support but none of that is included in this patch. It should mostly be an NFC. Global ISel is still expected to use the underlying LLT as it needs, and are not expected to see unknown sizes for generic operations. Most of the changes are hopefully fairly mechanical, adding a lot of getValue() calls and protecting them with hasValue() where needed.
2024-02-10[GlobalISel][Mips] Global ISel for `brcond`darkbuck
- Enable equivalent between `brcond` and `G_BRCOND`. - Remove the manual selection of `G_BRCOND` in Mips. Revise test cases. Reviewers: petar-avramovic, bcardosolopes, arsenm Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/81306
2023-07-11[GlobalISel] Generalize `InstructionSelector` Match Tablespvanhout
Makes `InstructionSelector.h`/`InstructionSelectorImpl.h` generic so the match tables can also be used for the combiner. Some notes: - Coverage was made an optional parameter of `executeMatchTable`, combines won't use it for now. - `GIPFP_` -> `GICXXPred_` so it's more generic. Those are just C++ predicates and aren't PatFrag-specific. - Pass the MatcherState directly to testMIPredicate_MI, the combiner will need it. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D153755
2023-01-13[CodeGen][Target] Remove uses of ↵Craig Topper
Register::isPhysicalRegister/isVirtualRegister. NFC Use isPhysical/isVirtual methods.
2022-01-06[Target] Remove redundant member initialization (NFC)Kazu Hirata
Identified with readability-redundant-member-init.
2022-01-03Revert "[llvm] Remove redundant member initialization (NFC)"Kazu Hirata
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3. This patch causes gcc to issue a lot of warnings like: warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra]
2022-01-01[llvm] Remove redundant member initialization (NFC)Kazu Hirata
Identified with readability-redundant-member-init.
2021-10-04[APInt] Stop using soft-deprecated constructors and methods in llvm. NFC.Jay Foad
Stop using APInt constructors and methods that were soft-deprecated in D109483. This fixes all the uses I found in llvm, except for the APInt unit tests which should still test the deprecated methods. Differential Revision: https://reviews.llvm.org/D110807
2020-06-30Mips: Don't store MachineFunction in MipsFunctionInfoMatt Arsenault
It will soon be disallowed to depend on MachineFunction state on construction.
2020-03-31[Alignment][NFC] Transitionning more getMachineMemOperand call sitesGuillaume Chatelet
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, Jim, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77121
2020-03-27[Alignment][NFC] MachineMemOperand::getAlign/getBaseAlignGuillaume Chatelet
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dschuff, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, jrtc27, atanasyan, jfb, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76925
2020-02-19[MIPS GlobalISel] Select 4 byte unaligned load and storePetar Avramovic
Improve legality checks for load and store, 4 byte scalar load and store are now legal for all subtargets. During regbank selection 4 byte unaligned loads and stores for MIPS32r5 and older get mapped to gprb. Select 4 byte unaligned loads and stores for MIPS32r5. Fix tests that unintentionally had unaligned load or store. Differential Revision: https://reviews.llvm.org/D74624
2020-02-19[MIPS GlobalISel] RegBankSelect G_MERGE_VALUES and G_UNMERGE_VALUESPetar Avramovic
Consider large operands in G_MERGE_VALUES and G_UNMERGE_VALUES as Ambiguous during regbank selection. Introducing new InstType AmbiguousWithMergeOrUnmerge which will allow us to recognize whether to narrow scalar or use s64:fprb. This change exposed a bug when reusing data from TypeInfoForMF. Thus when Instr is about to get destroyed (using narrow scalar) clear its data in TypeInfoForMF. Internal data is saved based on Instr's address, and it will no longer be valid. Add detailed asserts for InstType and operand size. Generate generic instructions instead of MIPS target instructions during argument lowering and custom legalizer. Select G_UNMERGE_VALUES and G_MERGE_VALUES when proper banks are selected: {s32:gprb, s32:gprb, s64:fprb} for G_UNMERGE_VALUES and {s64:fprb, s32:gprb, s32:gprb} for G_MERGE_VALUES. Update tests. One improvement is when floating point argument in gpr(or two gprs) gets passed to another function through gpr unnecessary fpr-to-gpr moves are no longer generated. Differential Revision: https://reviews.llvm.org/D74623
2019-12-11[IR] Split out target specific intrinsic enums into separate headersReid Kleckner
This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320
2019-11-05[globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders
Summary: G_GEP is rather poorly named. It's a simple pointer+scalar addition and doesn't support any of the complexities of getelementptr. I therefore propose that we rename it. There's a G_PTR_MASK so let's follow that convention and go with G_PTR_ADD Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69734
2019-11-03[mips] Split long lines in the code. NFCSimon Atanasyan
2019-11-01[MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off ↵Fangrui Song
builds after D69663
2019-11-01[MIPS GlobalISel] Improve reg bank handling in MipsInstructionSelectorPetar Avramovic
Introduce helper methods and refactor pieces of code related to register banks in MipsInstructionSelector. Add a few detailed asserts in order to get a better overview of LLT, register bank combinations that are supported at the moment and reduce need to look at other files. Differential Revision: https://reviews.llvm.org/D69663
2019-10-23[MIPS GlobalISel] Select MSA vector generic and builtin mulPetar Avramovic
Select vector G_MUL for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. Manual selection of G_MUL is now done for gprb only. __builtin_msa_mulv_<format> will be transformed into G_MUL in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69310
2019-10-15[MIPS GlobalISel] Add MSA registers to fprb. Select vector load, storePetar Avramovic
Add vector MSA register classes to fprb, they are 128 bit wide. MSA instructions use the same registers for both integer and floating point operations. Therefore we only need to check for vector element size during legalization or instruction selection. Add helper function in MipsLegalizerInfo and switch to legalIf LegalizeRuleSet to keep legalization rules compact since they depend on MipsSubtarget and presence of MSA. fprb is assigned to all vector operands. Move selectLoadStoreOpCode to MipsInstructionSelector in order to reduce number of arguments. Differential Revision: https://reviews.llvm.org/D68867 llvm-svn: 374872
2019-09-23[MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopyPetar Avramovic
CC_Mips doesn't accept vararg functions for O32, so we have to explicitly use CC_Mips_FixedArg. For lowerCall we now properly figure out whether callee function is vararg or not, this has no effect for O32 since we always use CC_Mips_FixedArg. For lower formal arguments we need to copy arguments in register to stack and save pointer to start for argument list into MipsMachineFunction object so that G_VASTART could use it during instruction select. For vacopy we need to copy content from one vreg to another, load and store are used for that purpose. Differential Revision: https://reviews.llvm.org/D67756 llvm-svn: 372555
2019-09-12[MIPS GlobalISel] Select indirect branchPetar Avramovic
Select G_BRINDIRECT for MIPS32. Differential Revision: https://reviews.llvm.org/D67441 llvm-svn: 371730
2019-09-12[MIPS GlobalISel] Select G_IMPLICIT_DEFPetar Avramovic
G_IMPLICIT_DEF is used for both integer and floating point implicit-def. Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo. Select G_IMPLICIT_DEF for MIPS32. Differential Revision: https://reviews.llvm.org/D67439 llvm-svn: 371727
2019-09-05[MIPS GlobalISel] Select G_FENCEPetar Avramovic
G_FENCE comes form fence instruction. For MIPS fence is generated in AtomicExpandPass when atomic instruction gets surrounded with fence instruction when needed. G_FENCE arguments don't have LLT, because of that there is no job for legalizer and regbankselect. Instruction select G_FENCE for MIPS32. Differential Revision: https://reviews.llvm.org/D67181 llvm-svn: 371056
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
2019-08-13[GlobalISel] Make the InstructionSelector instance non-const, allowing state ↵Amara Emerson
to be maintained. Currently we can't keep any state in the selector object that we get from subtarget. As a result we have to plumb through all our variables through multiple functions. This change makes it non-const and adds a virtual init() method to allow further state to be captured for each target. AArch64 makes use of this in this patch to cache a call to hasFnAttribute() which is expensive to call, and is used on each selection of G_BRCOND. Differential Revision: https://reviews.llvm.org/D65984 llvm-svn: 368652
2019-08-08[MIPS GlobalISel] Select jump_table and brjtPetar Avramovic
G_JUMP_TABLE and G_BRJT appear from translation of switch statement. Select these two instructions for MIPS32, both pic and non-pic. Differential Revision: https://reviews.llvm.org/D65861 llvm-svn: 368274
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders
llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-08-01[MIPS GlobalISel] Fold load/store + G_GEP + G_CONSTANTPetar Avramovic
Fold load/store + G_GEP + G_CONSTANT when immediate in G_CONSTANT fits into 16 bit signed integer. Differential Revision: https://reviews.llvm.org/D65507 llvm-svn: 367535
2019-07-26[MIPS GlobalISel] Select inttoptr and ptrtointPetar Avramovic
Select G_INTTOPTR and G_PTRTOINT for MIPS32. Differential Revision: https://reviews.llvm.org/D65217 llvm-svn: 367104
2019-07-10[MIPS GlobalISel] Select float and double phiPetar Avramovic
Select float and double phi for MIPS32. Differential Revision: https://reviews.llvm.org/D64420 llvm-svn: 365627
2019-07-10[MIPS GlobalISel] Select float and double load and storePetar Avramovic
Select float and double load and store for MIPS32. Differential Revision: https://reviews.llvm.org/D64419 llvm-svn: 365626
2019-06-24GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault
Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
2019-06-21[MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off ↵Fangrui Song
builds after D63541 llvm-svn: 364003
2019-06-20[MIPS GlobalISel] Select floating point to integer conversionsPetar Avramovic
Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
2019-06-06[MIPS GlobalISel] Select fabsPetar Avramovic
Select G_FABS for MIPS32. Differential Revision: https://reviews.llvm.org/D62903 llvm-svn: 362690
2019-06-05[MIPS GlobalISel] Select fcmpPetar Avramovic
Select floating point compare for MIPS32. Differential Revision: https://reviews.llvm.org/D62721 llvm-svn: 362603
2019-05-31[MIPS GlobalISel] Handle position independent code Petar Avramovic
Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
2019-03-28[MIPS GlobalISel] Select float constantsPetar Avramovic
Select 32 and 64 bit float constants for MIPS32. Differential Revision: https://reviews.llvm.org/D59933 llvm-svn: 357183
2019-03-25[MIPS GlobalISel] Select copy for arguments from FPRBRegBankPetar Avramovic
Move selectCopy into MipsInstructionSelector class. Select copy for arguments from FPRBRegBank for MIPS32. Differential Revision: https://reviews.llvm.org/D59644 llvm-svn: 356886
2019-03-15[MIPS GlobalISel] Improve selection of constantsPetar Avramovic
Certain 32 bit constants can be generated with a single instruction instead of two. Implement materialize32BitImm function for MIPS32. Differential Revision: https://reviews.llvm.org/D59369 llvm-svn: 356238
2019-03-07[MIPS GlobalISel] Fix mul operandsPetar Avramovic
Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355594
2019-03-01Revert "[MIPS GlobalISel] Fix mul operands"Vlad Tsyrklevich
This reverts commit r355178, it is causing ASan failures on the sanitizer bots. llvm-svn: 355219
2019-03-01[MIPS GlobalISel] Fix mul operandsPetar Avramovic
Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355178
2019-03-01[MIPS GlobalISel] Select G_UMULHPetar Avramovic
Legalize G_UMULO and select G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58714 llvm-svn: 355177
2019-02-14[MIPS GlobalISel] Select phi instruction for integers Petar Avramovic
Select G_PHI for integers for MIPS32. Differential Revision: https://reviews.llvm.org/D58183 llvm-svn: 354025
2019-02-14[MIPS GlobalISel] Select branch instructionsPetar Avramovic
Select G_BR and G_BRCOND for MIPS32. Unconditional branch G_BR does not have register operand, for that reason we only add tests. Since conditional branch G_BRCOND compares register to zero on MIPS32, explicit extension must be performed on i1 condition in order to set high bits to appropriate value. Differential Revision: https://reviews.llvm.org/D58182 llvm-svn: 354022
2019-02-08[MIPS GlobalISel] Select any extending load and truncating storePetar Avramovic
Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
2019-01-24[MIPS GlobalISel] Select zero extending and sign extending loadPetar Avramovic
Select zero extending and sign extending load for MIPS32. Use size from MachineMemOperand to determine number of bytes to load. Differential Revision: https://reviews.llvm.org/D57099 llvm-svn: 352038
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