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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
AgeCommit message (Expand)Author
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan
2023-06-29[AMDGPU] Reserve SGPR pair when long branches are presentBrendon Cahoon
2023-04-08AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnableMatt Arsenault
2023-03-08[AMDGPU] Extend WorkGroupID* codegen for compute shadersChristudasan Devadasan
2022-12-21CodeGen: Don't lazily construct MachineFunctionInfoMatt Arsenault
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan
2022-12-17Fix unused variable warning in release build, NFC.Haojian Wu
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-12-17[AMDGPU] Preserve only the inactive lanes of scratch vgprsChristudasan Devadasan
2022-12-17[AMDGPU][SIFrameLowering] Unify PEI SGPR spill saves and restoresChristudasan Devadasan
2022-12-17[AMDGPU] Separate out SGPR spills to VGPR lanes during PEIChristudasan Devadasan
2022-12-17[AMDGPU] Add WWM reserved VGPRs to WWMSpillsChristudasan Devadasan
2022-12-17[AMDGPU] Callee must always spill writelane VGPRsChristudasan Devadasan
2022-12-16[AMDGPU][SIFrameLowering] Mark VGPR used for AGPR spills as reservedJeffrey Byrnes
2022-12-13[CodeGen] llvm::Optional => std::optionalFangrui Song
2022-12-06[YAML] Convert Optional to std::optionalKrzysztof Parzyszek
2022-12-05Remove unused #include "llvm/ADT/Optional.h"Fangrui Song
2022-12-02[Target] Use std::nullopt instead of None (NFC)Kazu Hirata
2022-11-30AMDGPU: Remove ImagePSV and move images to addrspace 7Nicolai Hähnle
2022-11-29AMDGPU: Remove BufferPseudoSourceValueNicolai Hähnle
2022-11-02AMDGPU: Directly pass Function to mayUseAGPRsMatt Arsenault
2022-09-28[AMDGPU] Move SIModeRegisterDefaults to SI MFIStanislav Mekhanoshin
2022-09-26Revert "[AMDGPU] Move SIModeRegisterDefaults to SI MFI"Vitaly Buka
2022-09-26[AMDGPU] Move SIModeRegisterDefaults to SI MFIStanislav Mekhanoshin
2022-07-19[amdgpu] Implement lds kernel id intrinsicJon Chesterfield
2022-06-22[Alignment] Use Align for MaxKernArgAlignGuillaume Chatelet
2022-06-07llvm-reduce: Add cloning of target MachineFunctionInfoMatt Arsenault
2022-06-07AMDGPU: Make PSV instances static membersMatt Arsenault
2022-06-02AMDGPU: Move SpilledReg from MFI to SIRegisterInfoMatt Arsenault
2022-04-21[AMDGPU] On gfx908, reserve VGPR for AGPR copy based on register budget.hsmahesha
2022-04-19AMDGPU: Serialize VGPRForAGPRCopyMatt Arsenault
2022-04-19AMDGPU: Fix allocating GDS globals to LDS offsetsMatt Arsenault
2022-04-19AMDGPU: Serialize a few more MachineFunctionInfo fields in MIRMatt Arsenault
2022-04-19AMDGPU: Serialize gds size in MIRMatt Arsenault
2022-04-19AMDGPU: Serialize WWM registersMatt Arsenault
2022-04-19AMDGPU: Defer creation of WWM VGPR spill slotsMatt Arsenault
2022-04-14[AMDGPU][NFC] Organize code around reserving VGPR32 for AGPR copy.hsmahesha
2022-03-28[AMDGPU][NFC]: Remove unnecessary MFI functionsChangpeng Fang
2022-02-25[AMDGPU][NFC]: Emit metadata for hidden_heap_v1 kernargChangpeng Fang
2022-02-18[AMDGPU][NFC] Fix typosSebastian Neubauer
2022-02-11[AMDGPU] replace hostcall module flag with function attributeSameer Sahasrabuddhe
2022-02-08[AMDGPU] Select VGPR versions of MFMA if possibleStanislav Mekhanoshin
2022-02-02AMDGPU: Add second emergency slot for SGPR to vmem for large framesMatt Arsenault
2022-01-18AMDGPU: Avoid enabling kernel workitem IDs with reqd_work_group_sizeMatt Arsenault
2022-01-11[AMDGPU] Do not reserve any VGPR for SGPR spillsAustin Kerbow
2021-12-23[AMDGPU] Don't remove VGPR to AGPR dead spills from frame infoBrendon Cahoon
2021-12-10AMDGPU: Remove fixed function ABI optionMatt Arsenault
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