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path: root/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
AgeCommit message (Expand)Author
2020-08-20[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegisterJay Foad
2020-07-24AMDGPU: Skip other terminators before inserting s_cbranch_exec[n]zMatt Arsenault
2020-07-03[AMDGPU] Insert PS early exit at end of control flowCarl Ritson
2020-07-03Revert "[AMDGPU] Insert PS early exit at end of control flow"Carl Ritson
2020-07-03[AMDGPU] Insert PS early exit at end of control flowCarl Ritson
2020-04-07[AMDGPU] Limit endcf-collapase to simple ifStanislav Mekhanoshin
2020-04-06[AMDGPU] Fix inaccurate commentsJay Foad
2020-03-13[AMDGPU] Fix endcf collapseStanislav Mekhanoshin
2020-03-13[AMDGPU] Disable endcf collapseStanislav Mekhanoshin
2020-03-12[AMDGPU] Simplify nested SI_END_CFStanislav Mekhanoshin
2020-02-09AMDGPU: Fix SI_IF lowering when the save exec reg has terminator usesMatt Arsenault
2020-01-22Resubmit: [AMDGPU] Invert the handling of skip insertion.cdevadas
2020-01-21Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle
2020-01-15[AMDGPU] Invert the handling of skip insertion.cdevadas
2019-11-26[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer...vpykhtin
2019-09-17[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. FixedAlexander Timofeev
2019-09-13Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev
2019-09-10[AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev
2019-08-20Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"Matt Arsenault
2019-08-18AMDGPU: Fix iterator error when lowering SI_END_CFMatt Arsenault
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders
2019-08-01Reapply "AMDGPU: Split block for si_end_cf"Matt Arsenault
2019-06-24CodeGen: Introduce a class for registersMatt Arsenault
2019-06-16[AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin
2019-04-27Revert "AMDGPU: Split block for si_end_cf"Mark Searles
2019-04-03AMDGPU: Split block for si_end_cfMatt Arsenault
2019-03-05AMDGPU: Preserve undef flag when expanding SI_IFMatt Arsenault
2019-02-22AMDGPU: Use removeAllRegUnitsForPhysRegMatt Arsenault
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2018-10-31AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-06-12[AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'Mark Searles
2018-05-25[AMDGPU] Fixed incorrect break from loopTim Renouf
2018-05-22AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard
2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl
2017-12-13Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
2017-10-24AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak
2017-08-04[AMDGPU] Preserve inverted bit in SI_IF in presence of SI_KILLStanislav Mekhanoshin
2017-07-26[AMDGPU] Optimize SI_IF lowering for simple if regionsStanislav Mekhanoshin
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth
2017-01-20[AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; oth...Eugene Zelenko
2017-01-19[AMDGPU] Add exec copy to LiveIntervals in SILowerControlFlow::emitElseStanislav Mekhanoshin
2017-01-13[CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus
2016-11-28[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition ...Stanislav Mekhanoshin
2016-11-22[AMDGPU] Fix multiple vreg definitions in si-lower-control-flowStanislav Mekhanoshin
2016-10-01Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini
2016-09-29AMDGPU: Partially fix control flow at -O0Matt Arsenault
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