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path: root/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
AgeCommit message (Expand)Author
2025-11-21[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)Jay Foad
2025-11-14AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)Matt Arsenault
2025-11-14AMDGPU: Constrain readfirstlane operand to vgpr_32 (#168001)Matt Arsenault
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad
2025-09-16[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)Carl Ritson
2025-09-08[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)Stanislav Mekhanoshin
2025-08-18[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)Kazu Hirata
2025-07-18[AMDGPU] Fix sgpr to vreg_1 copy analysis (#149181)Jorn Tuyls
2025-07-18AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold (#149263)Matt Arsenault
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen
2025-05-30[AMDGPU] Fix SIFixSGPRCopies handling of STRICT_WWM and friends (#142122)Jay Foad
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi
2025-05-05[AMDGPU][True16][CodeGen] readfirstlane for vgpr16 copy to sgpr32 (#118037)Brox Chen
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault
2025-03-05AMDGPU: Fix trying to query end iterator for DebugLoc (#129886)Matt Arsenault
2025-02-27AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (#128903)Matt Arsenault
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad
2024-09-24[AMDGPU] Default-initialize uninitialized class member variables (#108428)Georgi Mirazchiyski
2024-09-11[AMDGPU] Make more use of getWaveMaskRegClass. NFC. (#108186)Jay Foad
2024-08-09AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (#102614)Matt Arsenault
2024-07-17[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)Jay Foad
2024-07-17[AMDGPU] Use range-based for loops. NFC. (#99047)Jay Foad
2024-07-16[AMDGPU] Use member initializers. NFC.Jay Foad
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result...paperchalice
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang
2024-03-10Add llvm::min/max_element and use it in llvm/ and mlir/ directories. (#84678)Justin Lebar
2023-10-31[AMDGPU] Fix nondeterminism in SIFixSGPRCopies (#70644)Jay Foad
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin
2023-10-24[AMDGPU] Fix subreg check in the SIFixSGPRCopies (#70007)Stanislav Mekhanoshin
2023-10-06Reland "AMDGPU: Duplicate instead of COPY constants from VGPR to SGPR (#66882)"Diana Picus
2023-09-25Revert "AMDGPU: Duplicate instead of COPY constants from VGPR to SGPR (#66882)"Diana Picus
2023-09-25AMDGPU: Duplicate instead of COPY constants from VGPR to SGPR (#66882)Diana
2023-09-18[AMDGPU] Fix non-deterministic iteration order in SIFixSGPRCopies (#66617)David Stuttard
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks
2023-04-10[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALUskc7
2023-02-07[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.Jay Foad
2022-12-20[AMDGPU] Replace getPhysRegClass with getPhysRegBaseClassCarl Ritson
2022-12-16[AMDGPU] Lower VGPR to physical SGPR COPY to S_MOV_B32 if VGPR contains the c...Alexander Timofeev
2022-12-14[AMDGPU] Stop using make_pair and make_tuple. NFC.Jay Foad
2022-09-19[AMDGPU] SIFixSGPRCopies reworking to use one pass over the MIR for analysis ...Alexander Timofeev
2022-09-12TableGen: Introduce generated getSubRegisterClass functionMatt Arsenault
2022-09-03[llvm] Use range-based for loops (NFC)Kazu Hirata
2022-08-28[Target] Qualify auto in range-based for loops (NFC)Kazu Hirata
2022-08-10Revert "[AMDGPU] SIFixSGPRCopies refactoring"Evgenii Stepanov
2022-08-10[AMDGPU] SIFixSGPRCopies refactoringalex-t
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