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path: root/llvm/lib/CodeGen/MIRParser/MIParser.cpp
AgeCommit message (Expand)Author
2018-09-28Revert r343317Luke Cheeseman
2018-09-28Reapply changes reverted by r343235Luke Cheeseman
2018-09-27Revert r343192 as an ubsan build is currently failingLuke Cheeseman
2018-09-27Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman
2018-09-26Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman
2018-09-26Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman
2018-09-11add IR flags to MIMichael Berg
2018-08-20Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek
2018-08-16[x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth
2018-08-16[MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth
2018-07-26CodeGen: Cleanup regmask construction; NFCMatthias Braun
2018-07-16[CodeGen] Fix inconsistent declaration parameter nameFangrui Song
2018-06-19[MIRParser] Update a diagnostic message to use the correct register sigil. NFCMatt Davis
2018-06-05[MIRParser] Add parser support for 'true' and 'false' i1s.Amara Emerson
2018-05-08[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin
2018-05-05[MIRPraser] Improve error checking for typed immediate operandsHeejin Ahn
2018-05-05[MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn
2018-05-03MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi
2018-03-13[MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih
2018-01-26[MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih
2018-01-09[MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun
2017-12-15[MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih
2017-12-13Remove redundant includes from lib/CodeGen.Michael Zolotukhin
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28[mir] Print/Parse both MOLoad and MOStore when they occur together.Daniel Sanders
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie
2017-11-02[AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih
2017-09-01[MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0Jessica Paquette
2017-08-23Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner
2017-07-13[MIR] Add support for printing and parsing target MMO flagsGeoff Berry
2017-07-11Enhance synchscope representationKonstantin Zhuravlyov
2017-06-27fix trivial typos, NFCHiroshi Inoue
2017-06-06[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko
2017-05-05MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun
2017-04-23Revert "[APInt] Fix a few places that use APInt::getRawData to operate within...Renato Golin
2017-04-23[APInt] Fix a few places that use APInt::getRawData to operate within the nor...Craig Topper
2017-03-19[MIR] Support Customed Register Mask and CSRsOren Ben Simhon
2017-02-13MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover
2017-01-20[MIRParser] Allow generic register specification on operand.Ahmed Bougacha
2017-01-18MIRParser: Allow regclass specification on operandMatthias Braun
2016-12-22[GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet
2016-12-22[MIRParser] Fix a typo in comment and error message.Quentin Colombet
2016-12-22[MIRParser] Non-generic virtual register may have a type.Quentin Colombet
2016-12-16[MIRParser] Add parsing hex literals of arbitrary size as unsigned integersKrzysztof Parzyszek
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