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Age	Commit message (Expand)	Author
2025-11-13	[clang-format] Recognize Verilog DPI export and import (#165595)	sstwcw
2025-10-18	[clang-format] Remove special handling of comments after brace/paren (#71672)	Björn Schäpers
2025-03-31	[clang-format] Recognize wait fork in Verilog (#132042)	sstwcw
2024-11-20	[clang-format] Stop crashing on slightly off Verilog module headers (#116000)	sstwcw
2024-10-14	[clang-format] Stop crashing when formatting Verilog (#112043)	sstwcw
2024-06-17	[clang-format] Handle Verilog delay control (#95703)	sstwcw
2024-05-20	[clang-format][NFC] Remove redundnat llvm::, clang::, etc.	Owen Pan
2024-01-15	[clang-format] Stop aligning the to continuation lines (#76378)	sstwcw
2023-12-02	[clang-format] Add space in Verilog tagged unions (#71354)	sstwcw
2023-11-29	[clang-format] Indent Verilog case statements with comments (#71353)	sstwcw
2023-11-29	[clang-format] Add spaces around the Verilog implication operator (#71352)	sstwcw
2023-10-27	[clang-format][NFC] Remove more extraneous newlines in unit tests	Owen Pan
2023-09-21	[clang-format] Don't split "DPI"/"DPI-C" in Verilog imports (#66951)	Arthur Eubanks
2023-09-16	[clang-format] Properly indent lines inside Verilog case structure (#65861)	sstwcw
2023-09-05	[clang-format] Break long string literals in C#, etc.	sstwcw
2023-08-24	Revert "[clang-format] Break long string literals in C#, etc."	David Spickett
2023-08-24	[clang-format] Break long string literals in C#, etc.	sstwcw
2023-07-24	[clang-format] Add SpacesInParens with SpacesInParensOptions	Gedare Bloom
2023-06-29	[clang-format] Indent Verilog struct literal on new line	sstwcw
2023-05-16	[clang-format] Stop comment disrupting indentation of Verilog ports	sstwcw
2023-05-07	[clang-format] Don't indent Verilog `begin` keyword on its own line	sstwcw
2023-05-07	[clang-format] Recognize Verilog edge identifiers	sstwcw
2023-04-30	[clang-format] Recognize Verilog type dimension in module header	sstwcw
2023-04-16	[clang-format] Handle Verilog assertions and loops	sstwcw
2023-04-04	[clang-format] Add option for having one port per line in Verilog	sstwcw
2023-04-01	[clang-format] Handle Verilog struct literals	sstwcw
2023-04-01	[clang-format] Handle enum in Verilog	sstwcw
2023-03-26	[clang-format] Don't squash Verilog escaped identifiers	sstwcw
2023-03-25	[clang-format] Handle Verilog assign statements	sstwcw
2023-03-25	[clang-format] More work on space around operators in Verilog	sstwcw
2023-03-19	[clang-format] Fix non-case colons in Verilog case lines	sstwcw
2023-03-14	[clang-format] Recognize Verilog always blocks	sstwcw
2023-02-20	[clang-format] Put ports on separate lines in Verilog module headers	sstwcw
2023-02-06	[clang-format] Recognize Verilog non-blocking assignment	sstwcw
2022-07-29	[clang-format] Handle Verilog attributes	sstwcw
2022-07-29	[clang-format] Handle Verilog case statements	sstwcw
2022-07-29	[clang-format] Handle Verilog user-defined primitives	sstwcw
2022-07-29	[clang-format] Handle Verilog modules	sstwcw
2022-07-29	[clang-format] Handle Verilog blocks	sstwcw
2022-07-29	[clang-format] Handle Verilog numbers and operators	sstwcw
2022-06-26	[clang-format] Handle Verilog preprocessor directives	sstwcw
2022-06-26	[clang-format] Parse Verilog if statements	sstwcw