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-rw-r--r--llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll10
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/pr95865.ll43
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/remat.ll57
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll66
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll28
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll12
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll24
7 files changed, 115 insertions, 125 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index 2b800c449953..3250821a9253 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -44,8 +44,9 @@ define <4 x i64> @m2_splat_with_tail(<4 x i64> %v1) vscale_range(2,2) {
; CHECK-LABEL: m2_splat_with_tail:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vrgather.vi v8, v10, 0
+; CHECK-NEXT: vrgather.vi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
ret <4 x i64> %res
@@ -98,8 +99,9 @@ define <4 x i64> @m2_splat_into_identity(<4 x i64> %v1) vscale_range(2,2) {
; CHECK-LABEL: m2_splat_into_identity:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vrgather.vi v8, v10, 0
+; CHECK-NEXT: vrgather.vi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
index a4c793b49d54..ab9849631663 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
@@ -36,7 +36,7 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: .cfi_offset s10, -96
; CHECK-NEXT: .cfi_offset s11, -104
; CHECK-NEXT: li a6, 0
-; CHECK-NEXT: li a7, 8
+; CHECK-NEXT: li s2, 8
; CHECK-NEXT: li t0, 12
; CHECK-NEXT: li s0, 4
; CHECK-NEXT: li t1, 20
@@ -45,7 +45,7 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: andi t3, a4, 1
-; CHECK-NEXT: li s2, 4
+; CHECK-NEXT: li t2, 4
; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader.i
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_2 Depth 2
@@ -53,9 +53,9 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
; CHECK-NEXT: mv t4, t1
-; CHECK-NEXT: mv t2, s2
+; CHECK-NEXT: mv t5, t2
; CHECK-NEXT: mv t6, t0
-; CHECK-NEXT: mv s3, a7
+; CHECK-NEXT: mv a7, s2
; CHECK-NEXT: mv s4, a6
; CHECK-NEXT: .LBB0_2: # %for.cond5.preheader.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -64,9 +64,9 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
; CHECK-NEXT: mv s5, t4
-; CHECK-NEXT: mv t5, t2
+; CHECK-NEXT: mv s6, t5
; CHECK-NEXT: mv s7, t6
-; CHECK-NEXT: mv s8, s3
+; CHECK-NEXT: mv s3, a7
; CHECK-NEXT: mv s9, s4
; CHECK-NEXT: .LBB0_3: # %for.cond9.preheader.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -75,9 +75,9 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
; CHECK-NEXT: mv s11, s5
-; CHECK-NEXT: mv s6, t5
+; CHECK-NEXT: mv a3, s6
; CHECK-NEXT: mv ra, s7
-; CHECK-NEXT: mv a5, s8
+; CHECK-NEXT: mv s8, s3
; CHECK-NEXT: mv s1, s9
; CHECK-NEXT: .LBB0_4: # %vector.ph.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -92,44 +92,45 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: # Parent Loop BB0_3 Depth=3
; CHECK-NEXT: # Parent Loop BB0_4 Depth=4
; CHECK-NEXT: # => This Inner Loop Header: Depth=5
-; CHECK-NEXT: add a4, a5, a1
-; CHECK-NEXT: add a3, s6, a1
-; CHECK-NEXT: addi a1, a1, 4
+; CHECK-NEXT: addi a5, a1, 4
+; CHECK-NEXT: add a4, s8, a1
+; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: vse32.v v8, (a4), v0.t
-; CHECK-NEXT: vse32.v v8, (a3), v0.t
-; CHECK-NEXT: bne a1, s0, .LBB0_5
+; CHECK-NEXT: vse32.v v8, (a1), v0.t
+; CHECK-NEXT: mv a1, a5
+; CHECK-NEXT: bne a5, s0, .LBB0_5
; CHECK-NEXT: # %bb.6: # %for.cond.cleanup15.i
; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=4
; CHECK-NEXT: addi s1, s1, 4
-; CHECK-NEXT: addi a5, a5, 4
+; CHECK-NEXT: addi s8, s8, 4
; CHECK-NEXT: addi ra, ra, 4
-; CHECK-NEXT: addi s6, s6, 4
+; CHECK-NEXT: addi a3, a3, 4
; CHECK-NEXT: andi s10, a0, 1
; CHECK-NEXT: addi s11, s11, 4
; CHECK-NEXT: beqz s10, .LBB0_4
; CHECK-NEXT: # %bb.7: # %for.cond.cleanup11.i
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=3
; CHECK-NEXT: addi s9, s9, 4
-; CHECK-NEXT: addi s8, s8, 4
+; CHECK-NEXT: addi s3, s3, 4
; CHECK-NEXT: addi s7, s7, 4
-; CHECK-NEXT: addi t5, t5, 4
+; CHECK-NEXT: addi s6, s6, 4
; CHECK-NEXT: andi a1, a2, 1
; CHECK-NEXT: addi s5, s5, 4
; CHECK-NEXT: beqz a1, .LBB0_3
; CHECK-NEXT: # %bb.8: # %for.cond.cleanup7.i
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=2
; CHECK-NEXT: addi s4, s4, 4
-; CHECK-NEXT: addi s3, s3, 4
+; CHECK-NEXT: addi a7, a7, 4
; CHECK-NEXT: addi t6, t6, 4
-; CHECK-NEXT: addi t2, t2, 4
+; CHECK-NEXT: addi t5, t5, 4
; CHECK-NEXT: addi t4, t4, 4
; CHECK-NEXT: beqz t3, .LBB0_2
; CHECK-NEXT: # %bb.9: # %for.cond.cleanup3.i
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: addi a6, a6, 4
-; CHECK-NEXT: addi a7, a7, 4
-; CHECK-NEXT: addi t0, t0, 4
; CHECK-NEXT: addi s2, s2, 4
+; CHECK-NEXT: addi t0, t0, 4
+; CHECK-NEXT: addi t2, t2, 4
; CHECK-NEXT: addi t1, t1, 4
; CHECK-NEXT: beqz a1, .LBB0_1
; CHECK-NEXT: # %bb.10: # %l.exit
diff --git a/llvm/test/CodeGen/RISCV/rvv/remat.ll b/llvm/test/CodeGen/RISCV/rvv/remat.ll
index 95bff27fe8ca..57f1977c27b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/remat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/remat.ll
@@ -314,10 +314,13 @@ define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, p
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
@@ -326,7 +329,7 @@ define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, p
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a1, a2, 3
; CHECK-NEXT: slli a2, a2, 3
@@ -334,15 +337,6 @@ define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, p
; CHECK-NEXT: vmv.v.i v0, 0
; CHECK-NEXT: .LBB8_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a5, a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a5, a4, 4
@@ -350,33 +344,23 @@ define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, p
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a5, a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: vand.vv v16, v0, v8
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vmsne.vi v24, v16, 0
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vand.vv v16, v0, v8
-; CHECK-NEXT: vmsne.vi v8, v16, 0
+; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a5, a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
+; CHECK-NEXT: slli a5, a4, 4
+; CHECK-NEXT: add a4, a5, a4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vand.vv v16, v24, v8
+; CHECK-NEXT: vmsne.vi v8, v16, 0
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -397,19 +381,22 @@ define i64 @dual_remat(i64 %0, <vscale x 16 x i64> %1, <vscale x 16 x i64> %2, p
; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a5, zero, e64, m8, ta, ma
-; CHECK-NEXT: vor.vv v16, v16, v8
+; CHECK-NEXT: vor.vv v0, v0, v8
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a5, a5, 3
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vor.vv v0, v0, v8
+; CHECK-NEXT: vor.vv v24, v24, v8
; CHECK-NEXT: beqz a4, .LBB8_1
; CHECK-NEXT: # %bb.2: # %middle.block
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index 386c73612879..f295bd8d74df 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -2258,18 +2258,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
; CHECK-RV32-NEXT: .LBB98_3: # %vector.body
; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-RV32-NEXT: mv a7, a6
-; CHECK-RV32-NEXT: slli t0, a6, 2
-; CHECK-RV32-NEXT: add a6, a6, a4
-; CHECK-RV32-NEXT: add t0, a0, t0
-; CHECK-RV32-NEXT: vl2re32.v v8, (t0)
-; CHECK-RV32-NEXT: sltu a7, a6, a7
-; CHECK-RV32-NEXT: add a5, a5, a7
-; CHECK-RV32-NEXT: xor a7, a6, a3
+; CHECK-RV32-NEXT: slli a7, a6, 2
+; CHECK-RV32-NEXT: add t0, a6, a4
+; CHECK-RV32-NEXT: add a7, a0, a7
+; CHECK-RV32-NEXT: vl2re32.v v8, (a7)
+; CHECK-RV32-NEXT: sltu a6, t0, a6
+; CHECK-RV32-NEXT: add a5, a5, a6
+; CHECK-RV32-NEXT: xor a6, t0, a3
; CHECK-RV32-NEXT: vand.vx v8, v8, a1
-; CHECK-RV32-NEXT: or a7, a7, a5
-; CHECK-RV32-NEXT: vs2r.v v8, (t0)
-; CHECK-RV32-NEXT: bnez a7, .LBB98_3
+; CHECK-RV32-NEXT: or t1, a6, a5
+; CHECK-RV32-NEXT: vs2r.v v8, (a7)
+; CHECK-RV32-NEXT: mv a6, t0
+; CHECK-RV32-NEXT: bnez t1, .LBB98_3
; CHECK-RV32-NEXT: # %bb.4: # %middle.block
; CHECK-RV32-NEXT: bnez a3, .LBB98_6
; CHECK-RV32-NEXT: .LBB98_5: # %for.body
@@ -2350,18 +2350,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_3: # %vector.body
; CHECK-ZVKB-NOZBB32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-ZVKB-NOZBB32-NEXT: mv a7, a6
-; CHECK-ZVKB-NOZBB32-NEXT: slli t0, a6, 2
-; CHECK-ZVKB-NOZBB32-NEXT: add a6, a6, a4
-; CHECK-ZVKB-NOZBB32-NEXT: add t0, a0, t0
-; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (t0)
-; CHECK-ZVKB-NOZBB32-NEXT: sltu a7, a6, a7
-; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a7
-; CHECK-ZVKB-NOZBB32-NEXT: xor a7, a6, a3
+; CHECK-ZVKB-NOZBB32-NEXT: slli a7, a6, 2
+; CHECK-ZVKB-NOZBB32-NEXT: add t0, a6, a4
+; CHECK-ZVKB-NOZBB32-NEXT: add a7, a0, a7
+; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (a7)
+; CHECK-ZVKB-NOZBB32-NEXT: sltu a6, t0, a6
+; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a6
+; CHECK-ZVKB-NOZBB32-NEXT: xor a6, t0, a3
; CHECK-ZVKB-NOZBB32-NEXT: vandn.vx v8, v8, a1
-; CHECK-ZVKB-NOZBB32-NEXT: or a7, a7, a5
-; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (t0)
-; CHECK-ZVKB-NOZBB32-NEXT: bnez a7, .LBB98_3
+; CHECK-ZVKB-NOZBB32-NEXT: or t1, a6, a5
+; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (a7)
+; CHECK-ZVKB-NOZBB32-NEXT: mv a6, t0
+; CHECK-ZVKB-NOZBB32-NEXT: bnez t1, .LBB98_3
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.4: # %middle.block
; CHECK-ZVKB-NOZBB32-NEXT: bnez a3, .LBB98_7
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_5: # %for.body.preheader
@@ -2444,18 +2444,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_3: # %vector.body
; CHECK-ZVKB-ZBB32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-ZVKB-ZBB32-NEXT: mv a7, a6
-; CHECK-ZVKB-ZBB32-NEXT: slli t0, a6, 2
-; CHECK-ZVKB-ZBB32-NEXT: add a6, a6, a4
-; CHECK-ZVKB-ZBB32-NEXT: add t0, a0, t0
-; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (t0)
-; CHECK-ZVKB-ZBB32-NEXT: sltu a7, a6, a7
-; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a7
-; CHECK-ZVKB-ZBB32-NEXT: xor a7, a6, a3
+; CHECK-ZVKB-ZBB32-NEXT: slli a7, a6, 2
+; CHECK-ZVKB-ZBB32-NEXT: add t0, a6, a4
+; CHECK-ZVKB-ZBB32-NEXT: add a7, a0, a7
+; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (a7)
+; CHECK-ZVKB-ZBB32-NEXT: sltu a6, t0, a6
+; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a6
+; CHECK-ZVKB-ZBB32-NEXT: xor a6, t0, a3
; CHECK-ZVKB-ZBB32-NEXT: vandn.vx v8, v8, a1
-; CHECK-ZVKB-ZBB32-NEXT: or a7, a7, a5
-; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (t0)
-; CHECK-ZVKB-ZBB32-NEXT: bnez a7, .LBB98_3
+; CHECK-ZVKB-ZBB32-NEXT: or t1, a6, a5
+; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (a7)
+; CHECK-ZVKB-ZBB32-NEXT: mv a6, t0
+; CHECK-ZVKB-ZBB32-NEXT: bnez t1, .LBB98_3
; CHECK-ZVKB-ZBB32-NEXT: # %bb.4: # %middle.block
; CHECK-ZVKB-ZBB32-NEXT: bnez a3, .LBB98_6
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_5: # %for.body
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
index 10440089cff1..ed6b7f1e6efb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
@@ -25,24 +25,24 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
; RV32-NEXT: li a6, 0
; RV32-NEXT: .LBB0_4: # %vector.body
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: mv t0, a7
-; RV32-NEXT: slli t1, a7, 2
-; RV32-NEXT: addi a7, a7, 8
-; RV32-NEXT: add t1, a1, t1
+; RV32-NEXT: slli t0, a7, 2
+; RV32-NEXT: addi t1, a7, 8
+; RV32-NEXT: add t0, a1, t0
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle32.v v8, (t1)
-; RV32-NEXT: sltu t0, a7, t0
-; RV32-NEXT: xor t1, a7, a5
-; RV32-NEXT: add a6, a6, t0
+; RV32-NEXT: vle32.v v8, (t0)
+; RV32-NEXT: sltu a7, t1, a7
+; RV32-NEXT: xor t0, t1, a5
+; RV32-NEXT: add a6, a6, a7
; RV32-NEXT: vmslt.vx v12, v8, a2
; RV32-NEXT: vcompress.vm v10, v8, v12
-; RV32-NEXT: vcpop.m t0, v12
-; RV32-NEXT: vsetvli zero, t0, e32, m2, ta, ma
+; RV32-NEXT: vcpop.m a7, v12
+; RV32-NEXT: vsetvli zero, a7, e32, m2, ta, ma
; RV32-NEXT: vse32.v v10, (a0)
-; RV32-NEXT: slli t0, t0, 2
-; RV32-NEXT: or t1, t1, a6
-; RV32-NEXT: add a0, a0, t0
-; RV32-NEXT: bnez t1, .LBB0_4
+; RV32-NEXT: slli a7, a7, 2
+; RV32-NEXT: or t0, t0, a6
+; RV32-NEXT: add a0, a0, a7
+; RV32-NEXT: mv a7, t1
+; RV32-NEXT: bnez t0, .LBB0_4
; RV32-NEXT: # %bb.5: # %middle.block
; RV32-NEXT: bne a5, a3, .LBB0_9
; RV32-NEXT: .LBB0_6: # %for.cond.cleanup
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index e8d89d4066e4..2293a1e6979f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -895,21 +895,21 @@ define void @coalesce_vl_clobber(ptr %p) {
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: .LBB43_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a3, a2, e8, mf8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: slli a3, a1, 32
-; CHECK-NEXT: vsetvli a1, a2, e8, mf8, ta, ma
+; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: srli a3, a3, 32
+; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vslideup.vx v10, v9, a3, v0.t
+; CHECK-NEXT: vslideup.vx v10, v9, a1, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vse32.v v10, (a0), v0.t
; CHECK-NEXT: li a2, 1
+; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: j .LBB43_1
entry:
br label %vector.body
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
index af3b0852a646..ead79fcf53d8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
@@ -102,20 +102,20 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV32-NEXT: .LBB0_13: # %vector.body
; RV32-NEXT: # Parent Loop BB0_10 Depth=1
; RV32-NEXT: # => This Inner Loop Header: Depth=2
-; RV32-NEXT: mv s0, t6
-; RV32-NEXT: add t6, a2, t6
-; RV32-NEXT: add s1, a4, s0
-; RV32-NEXT: vl2r.v v8, (t6)
-; RV32-NEXT: add s2, a0, s0
+; RV32-NEXT: add s0, a2, t6
+; RV32-NEXT: add s1, a4, t6
+; RV32-NEXT: vl2r.v v8, (s0)
+; RV32-NEXT: add s0, a0, t6
; RV32-NEXT: vl2r.v v10, (s1)
-; RV32-NEXT: add t6, s0, t2
-; RV32-NEXT: sltu s0, t6, s0
-; RV32-NEXT: add t5, t5, s0
-; RV32-NEXT: xor s0, t6, t4
+; RV32-NEXT: add s1, t6, t2
+; RV32-NEXT: sltu t6, s1, t6
+; RV32-NEXT: add t5, t5, t6
+; RV32-NEXT: xor t6, s1, t4
; RV32-NEXT: vaaddu.vv v8, v8, v10
-; RV32-NEXT: or s0, s0, t5
-; RV32-NEXT: vs2r.v v8, (s2)
-; RV32-NEXT: bnez s0, .LBB0_13
+; RV32-NEXT: or s2, t6, t5
+; RV32-NEXT: vs2r.v v8, (s0)
+; RV32-NEXT: mv t6, s1
+; RV32-NEXT: bnez s2, .LBB0_13
; RV32-NEXT: # %bb.14: # %middle.block
; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1
; RV32-NEXT: beq t4, a6, .LBB0_9
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 09:19:52 +0000