1 files changed, 36 insertions, 36 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
index 1ab63762ecbd..9f3596359a66 100644
--- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
@@ -5,22 +5,22 @@
 define amdgpu_kernel void @break_inserted_outside_of_loop(ptr addrspace(1) %out, i32 %a) {
 ; SI-LABEL: break_inserted_outside_of_loop:
 ; SI:       ; %bb.0: ; %main_body
-; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-NEXT:    s_load_dword s0, s[2:3], 0xb
 ; SI-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_and_b32_e32 v0, s2, v0
+; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v0, 1, v0
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; SI-NEXT:    s_mov_b64 s[2:3], 0
+; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:  .LBB0_1: ; %ENDIF
 ; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; SI-NEXT:    s_and_b64 s[4:5], exec, vcc
-; SI-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
-; SI-NEXT:    s_andn2_b64 exec, exec, s[2:3]
+; SI-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
+; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; SI-NEXT:    s_cbranch_execnz .LBB0_1
 ; SI-NEXT:  ; %bb.2: ; %ENDLOOP
-; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    v_mov_b32_e32 v0, 0
@@ -30,22 +30,22 @@ define amdgpu_kernel void @break_inserted_outside_of_loop(ptr addrspace(1) %out,
 ;
 ; FLAT-LABEL: break_inserted_outside_of_loop:
 ; FLAT:       ; %bb.0: ; %main_body
-; FLAT-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; FLAT-NEXT:    s_load_dword s0, s[2:3], 0x2c
 ; FLAT-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
 ; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT-NEXT:    v_and_b32_e32 v0, s2, v0
+; FLAT-NEXT:    v_and_b32_e32 v0, s0, v0
 ; FLAT-NEXT:    v_and_b32_e32 v0, 1, v0
 ; FLAT-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; FLAT-NEXT:    s_mov_b64 s[2:3], 0
+; FLAT-NEXT:    s_mov_b64 s[0:1], 0
 ; FLAT-NEXT:  .LBB0_1: ; %ENDIF
 ; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; FLAT-NEXT:    s_and_b64 s[4:5], exec, vcc
-; FLAT-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
-; FLAT-NEXT:    s_andn2_b64 exec, exec, s[2:3]
+; FLAT-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
+; FLAT-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; FLAT-NEXT:    s_cbranch_execnz .LBB0_1
 ; FLAT-NEXT:  ; %bb.2: ; %ENDLOOP
-; FLAT-NEXT:    s_or_b64 exec, exec, s[2:3]
-; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; FLAT-NEXT:    s_or_b64 exec, exec, s[0:1]
+; FLAT-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; FLAT-NEXT:    s_mov_b32 s3, 0xf000
 ; FLAT-NEXT:    s_mov_b32 s2, -1
 ; FLAT-NEXT:    v_mov_b32_e32 v0, 0
@@ -71,23 +71,23 @@ define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
 ; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT:    s_mov_b64 s[2:3], 0
+; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    s_mov_b64 s[4:5], 0
 ; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
 ; SI-NEXT:    s_cbranch_execz .LBB1_2
 ; SI-NEXT:  ; %bb.1: ; %else
-; SI-NEXT:    s_load_dword s0, s[0:1], 0x9
+; SI-NEXT:    s_load_dword s2, s[2:3], 0x9
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_cmp_eq_u32 s0, 0
-; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
-; SI-NEXT:    s_and_b64 s[4:5], s[0:1], exec
+; SI-NEXT:    s_cmp_eq_u32 s2, 0
+; SI-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
 ; SI-NEXT:  .LBB1_2: ; %endif
 ; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
 ; SI-NEXT:  .LBB1_3: ; %loop
 ; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
-; SI-NEXT:    s_and_b64 s[0:1], exec, s[4:5]
-; SI-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
-; SI-NEXT:    s_andn2_b64 exec, exec, s[2:3]
+; SI-NEXT:    s_and_b64 s[2:3], exec, s[4:5]
+; SI-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
+; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; SI-NEXT:    s_cbranch_execnz .LBB1_3
 ; SI-NEXT:  ; %bb.4: ; %exit
 ; SI-NEXT:    s_endpgm
@@ -96,23 +96,23 @@ define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {
 ; FLAT:       ; %bb.0: ; %entry
 ; FLAT-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
 ; FLAT-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; FLAT-NEXT:    s_mov_b64 s[2:3], 0
+; FLAT-NEXT:    s_mov_b64 s[0:1], 0
 ; FLAT-NEXT:    s_mov_b64 s[4:5], 0
 ; FLAT-NEXT:    s_and_saveexec_b64 s[6:7], vcc
 ; FLAT-NEXT:    s_cbranch_execz .LBB1_2
 ; FLAT-NEXT:  ; %bb.1: ; %else
-; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x24
+; FLAT-NEXT:    s_load_dword s2, s[2:3], 0x24
 ; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT-NEXT:    s_cmp_eq_u32 s0, 0
-; FLAT-NEXT:    s_cselect_b64 s[0:1], -1, 0
-; FLAT-NEXT:    s_and_b64 s[4:5], s[0:1], exec
+; FLAT-NEXT:    s_cmp_eq_u32 s2, 0
+; FLAT-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; FLAT-NEXT:    s_and_b64 s[4:5], s[2:3], exec
 ; FLAT-NEXT:  .LBB1_2: ; %endif
 ; FLAT-NEXT:    s_or_b64 exec, exec, s[6:7]
 ; FLAT-NEXT:  .LBB1_3: ; %loop
 ; FLAT-NEXT:    ; =>This Inner Loop Header: Depth=1
-; FLAT-NEXT:    s_and_b64 s[0:1], exec, s[4:5]
-; FLAT-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
-; FLAT-NEXT:    s_andn2_b64 exec, exec, s[2:3]
+; FLAT-NEXT:    s_and_b64 s[2:3], exec, s[4:5]
+; FLAT-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
+; FLAT-NEXT:    s_andn2_b64 exec, exec, s[0:1]
 ; FLAT-NEXT:    s_cbranch_execnz .LBB1_3
 ; FLAT-NEXT:  ; %bb.4: ; %exit
 ; FLAT-NEXT:    s_endpgm
@@ -166,12 +166,12 @@ declare float @llvm.fabs.f32(float) nounwind readnone
 define amdgpu_kernel void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {
 ; SI-LABEL: loop_land_info_assert:
 ; SI:       ; %bb.0: ; %entry
-; SI-NEXT:    s_load_dword s2, s[0:1], 0xa
+; SI-NEXT:    s_load_dword s0, s[2:3], 0xa
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_cmp_lt_i32 s2, 4
+; SI-NEXT:    s_cmp_lt_i32 s0, 4
 ; SI-NEXT:    s_cbranch_scc1 .LBB3_4
 ; SI-NEXT:  ; %bb.1: ; %for.cond.preheader
-; SI-NEXT:    s_load_dword s0, s[0:1], 0xc
+; SI-NEXT:    s_load_dword s0, s[2:3], 0xc
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_cmpk_lt_i32 s0, 0x3e8
 ; SI-NEXT:    s_cbranch_scc0 .LBB3_4
@@ -186,12 +186,12 @@ define amdgpu_kernel void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32
 ;
 ; FLAT-LABEL: loop_land_info_assert:
 ; FLAT:       ; %bb.0: ; %entry
-; FLAT-NEXT:    s_load_dword s2, s[0:1], 0x28
+; FLAT-NEXT:    s_load_dword s0, s[2:3], 0x28
 ; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT-NEXT:    s_cmp_lt_i32 s2, 4
+; FLAT-NEXT:    s_cmp_lt_i32 s0, 4
 ; FLAT-NEXT:    s_cbranch_scc1 .LBB3_4
 ; FLAT-NEXT:  ; %bb.1: ; %for.cond.preheader
-; FLAT-NEXT:    s_load_dword s0, s[0:1], 0x30
+; FLAT-NEXT:    s_load_dword s0, s[2:3], 0x30
 ; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLAT-NEXT:    s_cmpk_lt_i32 s0, 0x3e8
 ; FLAT-NEXT:    s_cbranch_scc0 .LBB3_4