diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll index d2712ac8e08a..ab2c0f468c1c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll @@ -10,6 +10,7 @@ declare void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %D0, <8 x i32> %D1, define amdgpu_ps void @tensor_load_to_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) { ; GFX1250-LABEL: tensor_load_to_lds: ; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19] ; GFX1250-NEXT: s_endpgm entry: @@ -20,6 +21,7 @@ entry: define amdgpu_ps void @tensor_load_to_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) { ; GFX1250-SDAG-LABEL: tensor_load_to_lds_vector: ; GFX1250-SDAG: ; %bb.0: ; %entry +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6 @@ -46,6 +48,7 @@ define amdgpu_ps void @tensor_load_to_lds_vector(<4 x i32> %D0, <8 x i32> %D1, < ; ; GFX1250-GISEL-LABEL: tensor_load_to_lds_vector: ; GFX1250-GISEL: ; %bb.0: ; %entry +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2 @@ -78,6 +81,7 @@ entry: define amdgpu_ps void @tensor_load_to_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) { ; GFX1250-LABEL: tensor_load_to_lds_d2: ; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS scope:SCOPE_SYS ; GFX1250-NEXT: s_endpgm entry: @@ -88,6 +92,7 @@ entry: define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) { ; GFX1250-SDAG-LABEL: tensor_load_to_lds_d2_vector: ; GFX1250-SDAG: ; %bb.0: ; %entry +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1 @@ -106,6 +111,7 @@ define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1 ; ; GFX1250-GISEL-LABEL: tensor_load_to_lds_d2_vector: ; GFX1250-GISEL: ; %bb.0: ; %entry +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2 @@ -129,6 +135,7 @@ entry: define amdgpu_ps void @tensor_store_from_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) { ; GFX1250-LABEL: tensor_store_from_lds: ; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV ; GFX1250-NEXT: s_endpgm entry: @@ -139,6 +146,7 @@ entry: define amdgpu_ps void @tensor_store_from_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) { ; GFX1250-SDAG-LABEL: tensor_store_from_lds_vector: ; GFX1250-SDAG: ; %bb.0: ; %entry +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6 @@ -165,6 +173,7 @@ define amdgpu_ps void @tensor_store_from_lds_vector(<4 x i32> %D0, <8 x i32> %D1 ; ; GFX1250-GISEL-LABEL: tensor_store_from_lds_vector: ; GFX1250-GISEL: ; %bb.0: ; %entry +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2 @@ -196,6 +205,7 @@ entry: define amdgpu_ps void @tensor_store_from_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) { ; GFX1250-LABEL: tensor_store_from_lds_d2: ; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11] ; GFX1250-NEXT: s_endpgm entry: @@ -206,6 +216,7 @@ entry: define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) { ; GFX1250-SDAG-LABEL: tensor_store_from_lds_d2_vector: ; GFX1250-SDAG: ; %bb.0: ; %entry +; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1 @@ -224,6 +235,7 @@ define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> ; ; GFX1250-GISEL-LABEL: tensor_store_from_lds_d2_vector: ; GFX1250-GISEL: ; %bb.0: ; %entry +; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1 ; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2 |