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authorJay Foad <jay.foad@amd.com>2022-06-07 10:41:50 +0100
committerJay Foad <jay.foad@amd.com>2022-06-07 19:06:28 +0100
commit4561352f7bd972939f19d7ff8462386c97b584ad (patch)
tree29c9637575897d19ee39c63162481e9cc0d177d8 /llvm/utils/TableGen/CodeEmitterGen.cpp
parentbccbf5276e6ee23a427b48d80ad42ff31575c1e7 (diff)
[CodeEmitter] Fix encoding wide instructions on big-endian hosts
For instructions wider than 64 bits the InstBits table is initialized in 64-bit chunks from APInt::getRawData, but it was being read with LoadIntFromMemory which is byte-based. Fix this by reading the table with the APInt constructor that takes an ArrayRef to the raw data instead. This is currently NFC for in-tree targets but fixes AMDGPU failures on big-endian hosts that were caused by D126483 until it was reverted. Differential Revision: https://reviews.llvm.org/D127195
Diffstat (limited to 'llvm/utils/TableGen/CodeEmitterGen.cpp')
-rw-r--r--llvm/utils/TableGen/CodeEmitterGen.cpp8
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index f446e5fe4414..8f96b7ffc279 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -482,14 +482,12 @@ void CodeEmitterGen::run(raw_ostream &o) {
// Emit initial function code
if (UseAPInt) {
int NumWords = APInt::getNumWords(BitWidth);
- int NumBytes = (BitWidth + 7) / 8;
o << " const unsigned opcode = MI.getOpcode();\n"
- << " if (Inst.getBitWidth() != " << BitWidth << ")\n"
- << " Inst = Inst.zext(" << BitWidth << ");\n"
<< " if (Scratch.getBitWidth() != " << BitWidth << ")\n"
<< " Scratch = Scratch.zext(" << BitWidth << ");\n"
- << " LoadIntFromMemory(Inst, (const uint8_t *)&InstBits[opcode * "
- << NumWords << "], " << NumBytes << ");\n"
+ << " Inst = APInt(" << BitWidth
+ << ", makeArrayRef(InstBits + opcode * " << NumWords << ", " << NumWords
+ << "));\n"
<< " APInt &Value = Inst;\n"
<< " APInt &op = Scratch;\n"
<< " switch (opcode) {\n";