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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-03-04 21:14:08 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2023-04-08 07:05:35 -0400 |
| commit | 7ac3ab34cb7aa3da1ff1b0c024a8767e089519cd (patch) | |
| tree | bb079bbb0ea4da7da49a37937b1087561de4962e /llvm/test/CodeGen/MIR/AMDGPU | |
| parent | 4bd3fda5124962e318f21b60e7e8f7c587dd31d6 (diff) | |
AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnable
Resuming any mir test for a pixel shader would assert in the AsmPrinter.
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU')
3 files changed, 29 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll index acff981f9850..1cf3699240d4 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll @@ -26,6 +26,8 @@ ; AFTER-PEI-NEXT: workGroupIDX: { reg: '$sgpr6' } ; AFTER-PEI-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } ; AFTER-PEI-NEXT: workItemIDX: { reg: '$vgpr0' } +; AFTER-PEI-NEXT: psInputAddr: 0 +; AFTER-PEI-NEXT: psInputEnable: 0 ; AFTER-PEI-NEXT: mode: ; AFTER-PEI-NEXT: ieee: true ; AFTER-PEI-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index 6d4c60eb221d..fa8607dc1306 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -36,6 +36,8 @@ # FULL-NEXT: workItemIDX: { reg: '$vgpr0' } # FULL-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +# FULL-NEXT: psInputAddr: 0 +# FULL-NEXT: psInputEnable: 0 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -134,6 +136,8 @@ body: | # FULL-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } # FULL-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +# FULL-NEXT: psInputAddr: 0 +# FULL-NEXT: psInputEnable: 0 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -203,6 +207,8 @@ body: | # FULL-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } # FULL-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +# FULL-NEXT: psInputAddr: 0 +# FULL-NEXT: psInputEnable: 0 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -273,6 +279,8 @@ body: | # FULL-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } # FULL-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +# FULL-NEXT: psInputAddr: 0 +# FULL-NEXT: psInputEnable: 0 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index a3ed1f25ebd9..7d365faa336f 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -30,6 +30,8 @@ ; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } +; CHECK-NEXT: psInputAddr: 0 +; CHECK-NEXT: psInputEnable: 0 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -70,6 +72,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } ; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } +; CHECK-NEXT: psInputAddr: 1 +; CHECK-NEXT: psInputEnable: 1 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: false ; CHECK-NEXT: dx10-clamp: true @@ -87,6 +91,16 @@ define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ret void } +; CHECK-LABEL: {{^}}name: ps_shader_ps_input_enable +; CHECK: machineFunctionInfo: +; CHECK: psInputAddr: 36983 +; CHECK-NEXT: psInputEnable: 1{{$}} +define amdgpu_ps void @ps_shader_ps_input_enable(i32 %arg0, i32 inreg %arg1) #7 { + %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0 + atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst + ret void +} + ; CHECK-LABEL: {{^}}name: gds_size_shader ; CHECK: gdsSize: 4096 define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 { @@ -124,6 +138,8 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 { ; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } ; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } ; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +; CHECK-NEXT: psInputAddr: 0 +; CHECK-NEXT: psInputEnable: 0 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -170,6 +186,8 @@ define void @function() { ; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } ; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } ; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } +; CHECK-NEXT: psInputAddr: 0 +; CHECK-NEXT: psInputEnable: 0 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -251,3 +269,4 @@ attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" } attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } attributes #5 = { "amdgpu-gds-size"="4096" } attributes #6 = { convergent nounwind readnone willreturn } +attributes #7 = { "InitialPSInputAddr"="36983" } |