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| author | tyb0807 <sontuan.vu119@gmail.com> | 2025-11-22 14:03:14 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-22 14:03:14 -0800 |
| commit | 29d1e1857d445ca9a6e60c69fe2e1e5b30767e62 (patch) | |
| tree | e4081d5f250ef763901b4e79401cd81e452125ab /llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir | |
| parent | ebb0c9c559b5809be491aa71cbe8235611081194 (diff) | |
[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)
- Support serialization of the number of allocated preload kernarg SGPRs
- Support serialization of the first preload kernarg SGPR allocated
Together they enable reconstructing correctly MIR with preload kernarg
SGPRs.
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir b/llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir new file mode 100644 index 000000000000..e7c174071195 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir @@ -0,0 +1,18 @@ +# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s + +--- +# CHECK: error: {{.*}} incorrect register class for field +name: kernarg_preload_wrong_register_class +tracksRegLiveness: true +machineFunctionInfo: + explicitKernArgSize: 4 + maxKernArgAlign: 4 + numKernargPreloadSGPRs: 1 + isEntryFunction: true + argumentInfo: + kernargSegmentPtr: { reg: '$sgpr0_sgpr1' } + firstKernArgPreloadReg: { reg: '$vgpr0' } # ERROR: VGPR instead of SGPR +body: | + bb.0: + S_ENDPGM 0 +... |