Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)

This reverts commit adaff46d087799072438dd744b038e6fd50a2d78. Drop the -O3 checks from default-attributes.hip. I don't know why they are different on some bots but reverting this is far too disruptive.
author: Matt Arsenault <Matthew.Arsenault@amd.com> 2024-07-15 09:59:07 +0400
committer: Matt Arsenault <arsenm2@gmail.com> 2024-07-15 11:51:44 +0400
commit: b1bcb7ca460fcd317bbc8309e14c8761bf8394e0 (patch)
tree: cf2636217534435b2de9783a7cf8e9325819e658 /llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
parent: 71051deff27928cff908ea794e09806eee662801 (diff)
1 files changed, 722 insertions, 626 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
index 7e15c07f9526..720e2ef10807 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
@@ -23,10 +23,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX6-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX6-NEXT:    ; implicit-def: $vgpr1
-; GFX6-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX6-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX6-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX6-NEXT:  ; %bb.1:
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0xd
 ; GFX6-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX6-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s4
@@ -34,8 +34,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX6-NEXT:  .LBB0_2:
-; GFX6-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
@@ -52,10 +52,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX8-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX8-NEXT:  ; %bb.1:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX8-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s4
@@ -63,8 +63,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB0_2:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    v_mad_u32_u24 v2, v0, 5, s2
@@ -81,10 +81,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX9-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX9-NEXT:  ; %bb.1:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX9-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s4
@@ -92,8 +92,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB0_2:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
@@ -109,10 +109,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX10W64-NEXT:  ; %bb.1:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -121,9 +121,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX10W64-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB0_2:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W64-NEXT:    s_mov_b32 null, 0
 ; GFX10W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX10W64-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10W64-NEXT:    v_mad_u32_u24 v0, v0, 5, s2
@@ -133,25 +134,26 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX10W32-LABEL: add_i32_constant:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX10W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
-; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s2, vcc_lo
+; GFX10W32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX10W32-NEXT:  ; %bb.1:
-; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX10W32-NEXT:    s_mul_i32 s3, s3, 5
-; GFX10W32-NEXT:    v_mov_b32_e32 v1, s3
+; GFX10W32-NEXT:    s_mul_i32 s1, s1, 5
+; GFX10W32-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W32-NEXT:    buffer_atomic_add v1, v2, s[4:7], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB0_2:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W32-NEXT:    s_mov_b32 null, 0
 ; GFX10W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10W32-NEXT:    v_mad_u32_u24 v0, v0, 5, s2
@@ -162,7 +164,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-LABEL: add_i32_constant:
 ; GFX11W64:       ; %bb.0: ; %entry
 ; GFX11W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -170,7 +172,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX11W64-NEXT:  ; %bb.1:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -179,8 +181,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB0_2:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W64-NEXT:    v_mov_b32_e32 v1, 0
@@ -194,25 +196,25 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX11W32-LABEL: add_i32_constant:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s2, exec_lo
-; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX11W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX11W32-NEXT:  ; %bb.1:
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11W32-NEXT:    s_mul_i32 s3, s3, 5
+; GFX11W32-NEXT:    s_mul_i32 s1, s1, 5
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_mov_b32_e32 v1, s3
+; GFX11W32-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[4:7], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB0_2:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W32-NEXT:    v_mov_b32_e32 v1, 0
@@ -227,7 +229,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-LABEL: add_i32_constant:
 ; GFX12W64:       ; %bb.0: ; %entry
 ; GFX12W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -235,7 +237,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX12W64-NEXT:  ; %bb.1:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX12W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -244,8 +246,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB0_2:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W64-NEXT:    v_mov_b32_e32 v1, 0
@@ -259,24 +261,24 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX12W32-LABEL: add_i32_constant:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s2, exec_lo
-; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s0, exec_lo
+; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX12W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX12W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB0_2
 ; GFX12W32-NEXT:  ; %bb.1:
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12W32-NEXT:    s_mul_i32 s3, s3, 5
-; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12W32-NEXT:    s_mul_i32 s1, s1, 5
+; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB0_2:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W32-NEXT:    v_mov_b32_e32 v1, 0
@@ -297,15 +299,15 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX6-LABEL: add_i32_uniform:
 ; GFX6:       ; %bb.0: ; %entry
 ; GFX6-NEXT:    s_mov_b64 s[4:5], exec
-; GFX6-NEXT:    s_load_dword s6, s[0:1], 0x11
+; GFX6-NEXT:    s_load_dword s6, s[2:3], 0x11
 ; GFX6-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
 ; GFX6-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX6-NEXT:    ; implicit-def: $vgpr1
-; GFX6-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX6-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX6-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX6-NEXT:  ; %bb.1:
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0xd
 ; GFX6-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mul_i32 s4, s6, s4
@@ -313,8 +315,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX6-NEXT:  .LBB1_2:
-; GFX6-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
@@ -327,16 +329,16 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX8-LABEL: add_i32_uniform:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX8-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX8-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX8-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX8-NEXT:  ; %bb.1:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_mul_i32 s4, s6, s4
@@ -344,8 +346,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB1_2:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
@@ -358,16 +360,16 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX9-LABEL: add_i32_uniform:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX9-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX9-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX9-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX9-NEXT:  ; %bb.1:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_mul_i32 s4, s6, s4
@@ -375,8 +377,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB1_2:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
@@ -388,16 +390,16 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX10W64-LABEL: add_i32_uniform:
 ; GFX10W64:       ; %bb.0: ; %entry
-; GFX10W64-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX10W64-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX10W64-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX10W64-NEXT:  ; %bb.1:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
@@ -406,9 +408,10 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX10W64-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB1_2:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W64-NEXT:    s_mov_b32 null, 0
 ; GFX10W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W64-NEXT:    v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3]
@@ -418,38 +421,38 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX10W32-LABEL: add_i32_uniform:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_load_dword s2, s[0:1], 0x44
+; GFX10W32-NEXT:    s_load_dword s0, s[2:3], 0x44
 ; GFX10W32-NEXT:    s_mov_b32 s4, exec_lo
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
+; GFX10W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX10W32-NEXT:  ; %bb.1:
-; GFX10W32-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W32-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX10W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX10W32-NEXT:    buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB1_2:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX10W32-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10W32-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10W32-NEXT:    v_mad_u64_u32 v[0:1], s2, s2, v0, s[4:5]
+; GFX10W32-NEXT:    v_mad_u64_u32 v[0:1], s0, s0, v0, s[4:5]
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10W32-NEXT:    global_store_dword v1, v0, s[0:1]
+; GFX10W32-NEXT:    global_store_dword v1, v0, s[2:3]
 ; GFX10W32-NEXT:    s_endpgm
 ;
 ; GFX11W64-LABEL: add_i32_uniform:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_load_b32 s6, s[0:1], 0x44
+; GFX11W64-NEXT:    s_load_b32 s6, s[2:3], 0x44
 ; GFX11W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -457,7 +460,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX11W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX11W64-NEXT:  ; %bb.1:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
@@ -466,8 +469,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX11W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB1_2:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
@@ -481,42 +484,42 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX11W32-LABEL: add_i32_uniform:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_load_b32 s2, s[0:1], 0x44
+; GFX11W32-NEXT:    s_load_b32 s0, s[2:3], 0x44
 ; GFX11W32-NEXT:    s_mov_b32 s4, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX11W32-NEXT:  ; %bb.1:
-; GFX11W32-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W32-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX11W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11W32-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB1_2:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX11W32-NEXT:    s_load_b64 s[2:3], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W32-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11W32-NEXT:    v_mad_u64_u32 v[1:2], null, s2, v0, s[4:5]
+; GFX11W32-NEXT:    v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5]
 ; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W32-NEXT:    global_store_b32 v0, v1, s[2:3]
 ; GFX11W32-NEXT:    s_nop 0
 ; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W32-NEXT:    s_endpgm
 ;
 ; GFX12W64-LABEL: add_i32_uniform:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_load_b32 s6, s[0:1], 0x44
+; GFX12W64-NEXT:    s_load_b32 s6, s[2:3], 0x44
 ; GFX12W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -524,7 +527,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX12W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX12W64-NEXT:  ; %bb.1:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
@@ -533,8 +536,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX12W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX12W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB1_2:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
@@ -548,32 +551,32 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX12W32-LABEL: add_i32_uniform:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_load_b32 s2, s[0:1], 0x44
+; GFX12W32-NEXT:    s_load_b32 s0, s[2:3], 0x44
 ; GFX12W32-NEXT:    s_mov_b32 s4, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX12W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB1_2
 ; GFX12W32-NEXT:  ; %bb.1:
-; GFX12W32-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W32-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX12W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s4
 ; GFX12W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB1_2:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX12W32-NEXT:    s_load_b64 s[2:3], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W32-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12W32-NEXT:    v_mad_co_u64_u32 v[0:1], null, s2, v0, s[4:5]
+; GFX12W32-NEXT:    v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
 ; GFX12W32-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX12W32-NEXT:    global_store_b32 v1, v0, s[2:3]
 ; GFX12W32-NEXT:    s_nop 0
 ; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W32-NEXT:    s_endpgm
@@ -586,8 +589,8 @@ entry:
 define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
 ; GFX6-LABEL: add_i32_varying_vdata:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_add v0, v1, s[4:7], 0 idxen glc
@@ -599,37 +602,37 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX8-LABEL: add_i32_varying_vdata:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_mov_b64 s[2:3], exec
+; GFX8-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX8-NEXT:    s_mov_b32 s4, 0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
 ; GFX8-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX8-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX8-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX8-NEXT:    s_mov_b32 m0, s5
 ; GFX8-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX8-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX8-NEXT:    v_writelane_b32 v1, s4, m0
 ; GFX8-NEXT:    s_add_i32 s4, s4, s8
-; GFX8-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
-; GFX8-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX8-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
+; GFX8-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX8-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX8-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr0
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX8-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX8-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX8-NEXT:  ; %bb.3:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB2_4:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s2, v1
@@ -641,37 +644,37 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX9-LABEL: add_i32_varying_vdata:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_mov_b64 s[2:3], exec
+; GFX9-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX9-NEXT:    s_mov_b32 s4, 0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
 ; GFX9-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX9-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX9-NEXT:    s_mov_b32 m0, s5
 ; GFX9-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX9-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX9-NEXT:    v_writelane_b32 v1, s4, m0
 ; GFX9-NEXT:    s_add_i32 s4, s4, s8
-; GFX9-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
-; GFX9-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX9-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX9-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX9-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr0
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX9-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX9-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX9-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX9-NEXT:  ; %bb.3:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB2_4:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
@@ -682,38 +685,39 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX10W64-LABEL: add_i32_varying_vdata:
 ; GFX10W64:       ; %bb.0: ; %entry
-; GFX10W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX10W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX10W64-NEXT:    s_mov_b32 s4, 0
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W64-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX10W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX10W64-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX10W64-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX10W64-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX10W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX10W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX10W64-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
+; GFX10W64-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
 ; GFX10W64-NEXT:    s_add_i32 s4, s4, s8
-; GFX10W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX10W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX10W64-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX10W64-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX10W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX10W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX10W64-NEXT:  ; %bb.3:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W64-NEXT:    buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB2_4:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W64-NEXT:    s_mov_b32 null, 0
 ; GFX10W64-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX10W64-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10W64-NEXT:    v_add_nc_u32_e32 v1, s2, v1
@@ -723,37 +727,38 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX10W32-LABEL: add_i32_varying_vdata:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX10W32-NEXT:    s_mov_b32 s2, 0
+; GFX10W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX10W32-NEXT:    s_mov_b32 s0, 0
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W32-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX10W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX10W32-NEXT:    s_ff1_i32_b32 s4, s3
+; GFX10W32-NEXT:    s_ff1_i32_b32 s4, s1
 ; GFX10W32-NEXT:    v_readlane_b32 s5, v0, s4
 ; GFX10W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX10W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX10W32-NEXT:    s_andn2_b32 s3, s3, s6
-; GFX10W32-NEXT:    s_add_i32 s2, s2, s5
-; GFX10W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX10W32-NEXT:    v_writelane_b32 v1, s0, s4
+; GFX10W32-NEXT:    s_andn2_b32 s1, s1, s6
+; GFX10W32-NEXT:    s_add_i32 s0, s0, s5
+; GFX10W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX10W32-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX10W32-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX10W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX10W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX10W32-NEXT:  ; %bb.3:
-; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10W32-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10W32-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W32-NEXT:    buffer_atomic_add v0, v2, s[4:7], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB2_4:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W32-NEXT:    s_mov_b32 null, 0
 ; GFX10W32-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX10W32-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10W32-NEXT:    v_add_nc_u32_e32 v1, s2, v1
@@ -763,178 +768,184 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX11W64-LABEL: add_i32_varying_vdata:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    s_mov_b32 s4, 0
-; GFX11W64-NEXT:    ; implicit-def: $vgpr1
+; GFX11W64-NEXT:    ; implicit-def: $vgpr0
 ; GFX11W64-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX11W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11W64-NEXT:    s_ctz_i32_b64 s5, s[2:3]
-; GFX11W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11W64-NEXT:    v_readlane_b32 s8, v0, s5
+; GFX11W64-NEXT:    s_ctz_i32_b64 s5, s[0:1]
+; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11W64-NEXT:    v_readlane_b32 s8, v1, s5
 ; GFX11W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
-; GFX11W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX11W64-NEXT:    s_and_not1_b64 s[2:3], s[2:3], s[6:7]
+; GFX11W64-NEXT:    v_writelane_b32 v0, s4, s5
+; GFX11W64-NEXT:    s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
 ; GFX11W64-NEXT:    s_add_i32 s4, s4, s8
-; GFX11W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX11W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX11W64-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX11W64-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX11W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX11W64-NEXT:    ; implicit-def: $vgpr0
-; GFX11W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX11W64-NEXT:    v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX11W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX11W64-NEXT:    ; implicit-def: $vgpr1
+; GFX11W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX11W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX11W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX11W64-NEXT:  ; %bb.3:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, s4
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W64-NEXT:    buffer_atomic_add_u32 v0, v2, s[8:11], 0 idxen glc
+; GFX11W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB2_4:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
-; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11W64-NEXT:    v_add_nc_u32_e32 v1, s2, v1
+; GFX11W64-NEXT:    v_add_nc_u32_e32 v0, s2, v0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W64-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11W64-NEXT:    s_nop 0
 ; GFX11W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W64-NEXT:    s_endpgm
 ;
 ; GFX11W32-LABEL: add_i32_varying_vdata:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s2, 0
-; GFX11W32-NEXT:    ; implicit-def: $vgpr1
+; GFX11W32-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s0, 0
+; GFX11W32-NEXT:    ; implicit-def: $vgpr0
 ; GFX11W32-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX11W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11W32-NEXT:    s_ctz_i32_b32 s4, s3
-; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11W32-NEXT:    v_readlane_b32 s5, v0, s4
+; GFX11W32-NEXT:    s_ctz_i32_b32 s4, s1
+; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11W32-NEXT:    v_readlane_b32 s5, v1, s4
 ; GFX11W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX11W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX11W32-NEXT:    s_and_not1_b32 s3, s3, s6
-; GFX11W32-NEXT:    s_add_i32 s2, s2, s5
-; GFX11W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX11W32-NEXT:    v_writelane_b32 v0, s0, s4
+; GFX11W32-NEXT:    s_and_not1_b32 s1, s1, s6
+; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11W32-NEXT:    s_add_i32 s0, s0, s5
+; GFX11W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX11W32-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX11W32-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11W32-NEXT:    ; implicit-def: $vgpr0
-; GFX11W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX11W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX11W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11W32-NEXT:    ; implicit-def: $vgpr1
+; GFX11W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX11W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX11W32-NEXT:  ; %bb.3:
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    buffer_atomic_add_u32 v0, v2, s[4:7], 0 idxen glc
+; GFX11W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[4:7], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB2_4:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11W32-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s2, v1
+; GFX11W32-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W32-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11W32-NEXT:    s_nop 0
 ; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W32-NEXT:    s_endpgm
 ;
 ; GFX12W64-LABEL: add_i32_varying_vdata:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    s_mov_b32 s4, 0
-; GFX12W64-NEXT:    ; implicit-def: $vgpr1
+; GFX12W64-NEXT:    ; implicit-def: $vgpr0
 ; GFX12W64-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX12W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX12W64-NEXT:    s_ctz_i32_b64 s5, s[2:3]
-; GFX12W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12W64-NEXT:    v_readlane_b32 s8, v0, s5
+; GFX12W64-NEXT:    s_ctz_i32_b64 s5, s[0:1]
+; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12W64-NEXT:    v_readlane_b32 s8, v1, s5
 ; GFX12W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
-; GFX12W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX12W64-NEXT:    s_and_not1_b64 s[2:3], s[2:3], s[6:7]
+; GFX12W64-NEXT:    v_writelane_b32 v0, s4, s5
+; GFX12W64-NEXT:    s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
 ; GFX12W64-NEXT:    s_add_co_i32 s4, s4, s8
-; GFX12W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX12W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX12W64-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX12W64-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX12W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX12W64-NEXT:    ; implicit-def: $vgpr0
-; GFX12W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX12W64-NEXT:    v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX12W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX12W64-NEXT:    ; implicit-def: $vgpr1
+; GFX12W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX12W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX12W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX12W64-NEXT:  ; %bb.3:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12W64-NEXT:    v_mov_b32_e32 v0, s4
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
-; GFX12W64-NEXT:    buffer_atomic_add_u32 v0, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX12W64-NEXT:    buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB2_4:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
-; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12W64-NEXT:    v_add_nc_u32_e32 v1, s2, v1
+; GFX12W64-NEXT:    v_add_nc_u32_e32 v0, s2, v0
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
-; GFX12W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W64-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12W64-NEXT:    s_nop 0
 ; GFX12W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W64-NEXT:    s_endpgm
 ;
 ; GFX12W32-LABEL: add_i32_varying_vdata:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s2, 0
-; GFX12W32-NEXT:    ; implicit-def: $vgpr1
+; GFX12W32-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s0, 0
+; GFX12W32-NEXT:    ; implicit-def: $vgpr0
 ; GFX12W32-NEXT:  .LBB2_1: ; %ComputeLoop
 ; GFX12W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT:    s_ctz_i32_b32 s4, s3
-; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12W32-NEXT:    v_readlane_b32 s5, v0, s4
+; GFX12W32-NEXT:    s_ctz_i32_b32 s4, s1
+; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12W32-NEXT:    v_readlane_b32 s5, v1, s4
 ; GFX12W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX12W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX12W32-NEXT:    s_and_not1_b32 s3, s3, s6
-; GFX12W32-NEXT:    s_add_co_i32 s2, s2, s5
-; GFX12W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX12W32-NEXT:    v_writelane_b32 v0, s0, s4
+; GFX12W32-NEXT:    s_and_not1_b32 s1, s1, s6
+; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12W32-NEXT:    s_add_co_i32 s0, s0, s5
+; GFX12W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX12W32-NEXT:    s_cbranch_scc1 .LBB2_1
 ; GFX12W32-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX12W32-NEXT:    ; implicit-def: $vgpr0
-; GFX12W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX12W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX12W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX12W32-NEXT:    ; implicit-def: $vgpr1
+; GFX12W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX12W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB2_4
 ; GFX12W32-NEXT:  ; %bb.3:
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12W32-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    buffer_atomic_add_u32 v0, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W32-NEXT:    buffer_atomic_add_u32 v1, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB2_4:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
-; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12W32-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s2, v1
+; GFX12W32-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W32-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12W32-NEXT:    s_nop 0
 ; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W32-NEXT:    s_endpgm
@@ -948,8 +959,8 @@ entry:
 define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
 ; GFX6-LABEL: add_i32_varying_vindex:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_add v1, v0, s[4:7], 0 idxen glc
@@ -961,9 +972,9 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX8-LABEL: add_i32_varying_vindex:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_add v2, v0, s[4:7], 0 idxen glc
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
@@ -974,9 +985,9 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX9-LABEL: add_i32_varying_vindex:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_add v1, v0, s[4:7], 0 idxen glc
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
@@ -986,9 +997,10 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX10-LABEL: add_i32_varying_vindex:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 1
-; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    buffer_atomic_add v1, v0, s[4:7], 0 idxen glc
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
@@ -996,33 +1008,67 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: add_i32_varying_vindex:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v1, 1
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], 0 idxen glc
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT:    s_nop 0
-; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: add_i32_varying_vindex:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12-NEXT:    v_mov_b32_e32 v1, 1
-; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT:    s_nop 0
-; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX12-NEXT:    s_endpgm
+; GFX11W64-LABEL: add_i32_varying_vindex:
+; GFX11W64:       ; %bb.0: ; %entry
+; GFX11W64-NEXT:    s_clause 0x1
+; GFX11W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX11W64-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, 1
+; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11W64-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], 0 idxen glc
+; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX11W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W64-NEXT:    s_nop 0
+; GFX11W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11W64-NEXT:    s_endpgm
+;
+; GFX11W32-LABEL: add_i32_varying_vindex:
+; GFX11W32:       ; %bb.0: ; %entry
+; GFX11W32-NEXT:    s_clause 0x1
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX11W32-NEXT:    v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11W32-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], 0 idxen glc
+; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX11W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W32-NEXT:    s_nop 0
+; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11W32-NEXT:    s_endpgm
+;
+; GFX12W64-LABEL: add_i32_varying_vindex:
+; GFX12W64:       ; %bb.0: ; %entry
+; GFX12W64-NEXT:    s_clause 0x1
+; GFX12W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W64-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, 1
+; GFX12W64-NEXT:    s_wait_kmcnt 0x0
+; GFX12W64-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W64-NEXT:    s_wait_loadcnt 0x0
+; GFX12W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W64-NEXT:    s_nop 0
+; GFX12W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12W64-NEXT:    s_endpgm
+;
+; GFX12W32-LABEL: add_i32_varying_vindex:
+; GFX12W32:       ; %bb.0: ; %entry
+; GFX12W32-NEXT:    s_clause 0x1
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W32-NEXT:    v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12W32-NEXT:    s_wait_kmcnt 0x0
+; GFX12W32-NEXT:    buffer_atomic_add_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W32-NEXT:    s_wait_loadcnt 0x0
+; GFX12W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W32-NEXT:    s_nop 0
+; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12W32-NEXT:    s_endpgm
 entry:
   %lane = call i32 @llvm.amdgcn.workitem.id.x()
   %old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0, i32 0)
@@ -1034,10 +1080,10 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ; GFX6-LABEL: add_i32_varying_offset:
 ; GFX6:       ; %bb.0: ; %entry
 ; GFX6-NEXT:    v_mov_b32_e32 v1, v0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s2, 0
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_mov_b32 s8, 0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_add v2, v[0:1], s[4:7], 0 idxen offen glc
@@ -1049,15 +1095,14 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX8-LABEL: add_i32_varying_offset:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s2, 0
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX8-NEXT:    s_mov_b32 s0, 0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, v0
-; GFX8-NEXT:    v_mov_b32_e32 v0, s2
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_add v2, v[0:1], s[4:7], 0 idxen offen glc
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
@@ -1066,27 +1111,27 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX9-LABEL: add_i32_varying_offset:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    s_mov_b32 s2, 0
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX9-NEXT:    s_mov_b32 s0, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v0
-; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_add v2, v[0:1], s[4:7], 0 idxen offen glc
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_dword v0, v2, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: add_i32_varying_offset:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10-NEXT:    s_mov_b32 s2, 0
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 1
-; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    buffer_atomic_add v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
@@ -1096,12 +1141,12 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX11W64-LABEL: add_i32_varying_offset:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W64-NEXT:    s_mov_b32 s2, 0
-; GFX11W64-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W64-NEXT:    s_mov_b32 s0, 0
+; GFX11W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W64-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 1
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W64-NEXT:    buffer_atomic_add_u32 v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
@@ -1113,12 +1158,12 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX11W32-LABEL: add_i32_varying_offset:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    s_mov_b32 s2, 0
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_mov_b32 s0, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s2
+; GFX11W32-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_and_b32 v1, 0x3ff, v0
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 1
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W32-NEXT:    buffer_atomic_add_u32 v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
@@ -1130,11 +1175,12 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX12W64-LABEL: add_i32_varying_offset:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W64-NEXT:    v_mov_b32_e32 v1, v0
+; GFX12W64-NEXT:    s_clause 0x1
+; GFX12W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
 ; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 1
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W64-NEXT:    buffer_atomic_add_u32 v2, v[0:1], s[4:7], null idxen offen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
@@ -1145,10 +1191,11 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX12W32-LABEL: add_i32_varying_offset:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, 0
+; GFX12W32-NEXT:    s_clause 0x1
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W32-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, 0x3ff, v0
 ; GFX12W32-NEXT:    v_mov_b32_e32 v2, 1
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W32-NEXT:    buffer_atomic_add_u32 v2, v[0:1], s[4:7], null idxen offen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
@@ -1171,10 +1218,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX6-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX6-NEXT:    ; implicit-def: $vgpr1
-; GFX6-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX6-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX6-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX6-NEXT:  ; %bb.1:
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0xd
 ; GFX6-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX6-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s4
@@ -1182,8 +1229,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX6-NEXT:  .LBB5_2:
-; GFX6-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
@@ -1201,10 +1248,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX8-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX8-NEXT:  ; %bb.1:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX8-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s4
@@ -1212,8 +1259,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB5_2:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1231,10 +1278,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX9-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX9-NEXT:  ; %bb.1:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX9-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s4
@@ -1242,8 +1289,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB5_2:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX9-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1260,10 +1307,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX10W64-NEXT:  ; %bb.1:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -1272,9 +1319,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX10W64-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB5_2:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W64-NEXT:    s_mov_b32 null, 0
 ; GFX10W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX10W64-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
 ; GFX10W64-NEXT:    v_mov_b32_e32 v1, 0
@@ -1285,25 +1333,26 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX10W32-LABEL: sub_i32_constant:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX10W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
-; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s2, vcc_lo
+; GFX10W32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX10W32-NEXT:  ; %bb.1:
-; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX10W32-NEXT:    s_mul_i32 s3, s3, 5
-; GFX10W32-NEXT:    v_mov_b32_e32 v1, s3
+; GFX10W32-NEXT:    s_mul_i32 s1, s1, 5
+; GFX10W32-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W32-NEXT:    buffer_atomic_sub v1, v2, s[4:7], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB5_2:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W32-NEXT:    s_mov_b32 null, 0
 ; GFX10W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX10W32-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, 0
@@ -1315,7 +1364,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-LABEL: sub_i32_constant:
 ; GFX11W64:       ; %bb.0: ; %entry
 ; GFX11W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1323,7 +1372,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX11W64-NEXT:  ; %bb.1:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -1332,8 +1381,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB5_2:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W64-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1348,25 +1397,25 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX11W32-LABEL: sub_i32_constant:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s2, exec_lo
-; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX11W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX11W32-NEXT:  ; %bb.1:
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11W32-NEXT:    s_mul_i32 s3, s3, 5
+; GFX11W32-NEXT:    s_mul_i32 s1, s1, 5
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_mov_b32_e32 v1, s3
+; GFX11W32-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[4:7], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB5_2:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX11W32-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1382,7 +1431,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-LABEL: sub_i32_constant:
 ; GFX12W64:       ; %bb.0: ; %entry
 ; GFX12W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1390,7 +1439,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX12W64-NEXT:  ; %bb.1:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX12W64-NEXT:    s_mul_i32 s4, s4, 5
@@ -1399,8 +1448,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB5_2:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W64-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1415,24 +1464,24 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
 ;
 ; GFX12W32-LABEL: sub_i32_constant:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s2, exec_lo
-; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s0, exec_lo
+; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s1, 0
 ; GFX12W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX12W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX12W32-NEXT:  ; %bb.1:
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    s_bcnt1_i32_b32 s3, s3
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_bcnt1_i32_b32 s1, s1
 ; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12W32-NEXT:    s_mul_i32 s3, s3, 5
-; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12W32-NEXT:    s_mul_i32 s1, s1, 5
+; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB5_2:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
 ; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX12W32-NEXT:    v_mul_u32_u24_e32 v0, 5, v0
@@ -1454,15 +1503,15 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX6-LABEL: sub_i32_uniform:
 ; GFX6:       ; %bb.0: ; %entry
 ; GFX6-NEXT:    s_mov_b64 s[4:5], exec
-; GFX6-NEXT:    s_load_dword s6, s[0:1], 0x11
+; GFX6-NEXT:    s_load_dword s6, s[2:3], 0x11
 ; GFX6-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
 ; GFX6-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX6-NEXT:    ; implicit-def: $vgpr1
-; GFX6-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX6-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX6-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX6-NEXT:  ; %bb.1:
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0xd
 ; GFX6-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mul_i32 s4, s6, s4
@@ -1470,8 +1519,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX6-NEXT:  .LBB6_2:
-; GFX6-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
@@ -1484,16 +1533,16 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX8-LABEL: sub_i32_uniform:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX8-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX8-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX8-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX8-NEXT:  ; %bb.1:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_mul_i32 s4, s6, s4
@@ -1501,8 +1550,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB6_2:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
@@ -1515,16 +1564,16 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX9-LABEL: sub_i32_uniform:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX9-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX9-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX9-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX9-NEXT:  ; %bb.1:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_mul_i32 s4, s6, s4
@@ -1532,8 +1581,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB6_2:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
@@ -1545,16 +1594,16 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX10W64-LABEL: sub_i32_uniform:
 ; GFX10W64:       ; %bb.0: ; %entry
-; GFX10W64-NEXT:    s_load_dword s6, s[0:1], 0x44
+; GFX10W64-NEXT:    s_load_dword s6, s[2:3], 0x44
 ; GFX10W64-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX10W64-NEXT:  ; %bb.1:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1563,8 +1612,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX10W64-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB6_2:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W64-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
@@ -1576,39 +1625,39 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX10W32-LABEL: sub_i32_uniform:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_load_dword s2, s[0:1], 0x44
+; GFX10W32-NEXT:    s_load_dword s0, s[2:3], 0x44
 ; GFX10W32-NEXT:    s_mov_b32 s4, exec_lo
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
+; GFX10W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX10W32-NEXT:  ; %bb.1:
-; GFX10W32-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W32-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX10W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX10W32-NEXT:    buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB6_2:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX10W32-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10W32-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX10W32-NEXT:    v_mul_lo_u32 v0, s0, v0
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX10W32-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX10W32-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX10W32-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10W32-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
-; GFX10W32-NEXT:    global_store_dword v1, v0, s[0:1]
+; GFX10W32-NEXT:    v_sub_nc_u32_e32 v0, s0, v0
+; GFX10W32-NEXT:    global_store_dword v1, v0, s[2:3]
 ; GFX10W32-NEXT:    s_endpgm
 ;
 ; GFX11W64-LABEL: sub_i32_uniform:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_load_b32 s6, s[0:1], 0x44
+; GFX11W64-NEXT:    s_load_b32 s6, s[2:3], 0x44
 ; GFX11W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1616,7 +1665,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX11W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX11W64-NEXT:  ; %bb.1:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1625,8 +1674,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX11W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB6_2:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W64-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
@@ -1641,43 +1690,43 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX11W32-LABEL: sub_i32_uniform:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_load_b32 s2, s[0:1], 0x44
+; GFX11W32-NEXT:    s_load_b32 s0, s[2:3], 0x44
 ; GFX11W32-NEXT:    s_mov_b32 s4, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX11W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX11W32-NEXT:  ; %bb.1:
-; GFX11W32-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX11W32-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX11W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX11W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11W32-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB6_2:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX11W32-NEXT:    s_load_b64 s[2:3], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX11W32-NEXT:    v_mul_lo_u32 v0, s0, v0
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX11W32-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX11W32-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11W32-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
-; GFX11W32-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11W32-NEXT:    v_sub_nc_u32_e32 v0, s0, v0
+; GFX11W32-NEXT:    global_store_b32 v1, v0, s[2:3]
 ; GFX11W32-NEXT:    s_nop 0
 ; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W32-NEXT:    s_endpgm
 ;
 ; GFX12W64-LABEL: sub_i32_uniform:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_load_b32 s6, s[0:1], 0x44
+; GFX12W64-NEXT:    s_load_b32 s6, s[2:3], 0x44
 ; GFX12W64-NEXT:    s_mov_b64 s[4:5], exec
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1685,7 +1734,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX12W64-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX12W64-NEXT:  ; %bb.1:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
@@ -1694,8 +1743,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ; GFX12W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX12W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB6_2:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W64-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
@@ -1710,33 +1759,33 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
 ;
 ; GFX12W32-LABEL: sub_i32_uniform:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_load_b32 s2, s[0:1], 0x44
+; GFX12W32-NEXT:    s_load_b32 s0, s[2:3], 0x44
 ; GFX12W32-NEXT:    s_mov_b32 s4, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
 ; GFX12W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX12W32-NEXT:    v_cmpx_eq_u32_e32 0, v0
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX12W32-NEXT:  ; %bb.1:
-; GFX12W32-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W32-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W32-NEXT:    s_bcnt1_i32_b32 s4, s4
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    s_mul_i32 s4, s2, s4
+; GFX12W32-NEXT:    s_mul_i32 s4, s0, s4
 ; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s4
 ; GFX12W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB6_2:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX12W32-NEXT:    s_load_b64 s[2:3], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX12W32-NEXT:    v_mul_lo_u32 v0, s0, v0
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
-; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX12W32-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX12W32-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12W32-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
-; GFX12W32-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX12W32-NEXT:    v_sub_nc_u32_e32 v0, s0, v0
+; GFX12W32-NEXT:    global_store_b32 v1, v0, s[2:3]
 ; GFX12W32-NEXT:    s_nop 0
 ; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W32-NEXT:    s_endpgm
@@ -1749,8 +1798,8 @@ entry:
 define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
 ; GFX6-LABEL: sub_i32_varying_vdata:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_sub v0, v1, s[4:7], 0 idxen glc
@@ -1762,37 +1811,37 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX8-LABEL: sub_i32_varying_vdata:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_mov_b64 s[2:3], exec
+; GFX8-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX8-NEXT:    s_mov_b32 s4, 0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1
 ; GFX8-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX8-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX8-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX8-NEXT:    s_mov_b32 m0, s5
 ; GFX8-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX8-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX8-NEXT:    v_writelane_b32 v1, s4, m0
 ; GFX8-NEXT:    s_add_i32 s4, s4, s8
-; GFX8-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
-; GFX8-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX8-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
+; GFX8-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX8-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX8-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr0
-; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX8-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX8-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX8-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX8-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX8-NEXT:  ; %bb.3:
-; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_sub v0, v2, s[8:11], 0 idxen glc
 ; GFX8-NEXT:  .LBB7_4:
-; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s2, v1
@@ -1804,37 +1853,37 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX9-LABEL: sub_i32_varying_vdata:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_mov_b64 s[2:3], exec
+; GFX9-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX9-NEXT:    s_mov_b32 s4, 0
 ; GFX9-NEXT:    ; implicit-def: $vgpr1
 ; GFX9-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX9-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX9-NEXT:    s_mov_b32 m0, s5
 ; GFX9-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX9-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX9-NEXT:    v_writelane_b32 v1, s4, m0
 ; GFX9-NEXT:    s_add_i32 s4, s4, s8
-; GFX9-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
-; GFX9-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX9-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX9-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX9-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX9-NEXT:    ; implicit-def: $vgpr0
-; GFX9-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX9-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX9-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX9-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX9-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX9-NEXT:  ; %bb.3:
-; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_sub v0, v2, s[8:11], 0 idxen glc
 ; GFX9-NEXT:  .LBB7_4:
-; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
@@ -1845,38 +1894,39 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX10W64-LABEL: sub_i32_varying_vdata:
 ; GFX10W64:       ; %bb.0: ; %entry
-; GFX10W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX10W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX10W64-NEXT:    s_mov_b32 s4, 0
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W64-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX10W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX10W64-NEXT:    s_ff1_i32_b64 s5, s[2:3]
+; GFX10W64-NEXT:    s_ff1_i32_b64 s5, s[0:1]
 ; GFX10W64-NEXT:    v_readlane_b32 s8, v0, s5
 ; GFX10W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
 ; GFX10W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX10W64-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[6:7]
+; GFX10W64-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[6:7]
 ; GFX10W64-NEXT:    s_add_i32 s4, s4, s8
-; GFX10W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX10W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX10W64-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX10W64-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX10W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX10W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX10W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX10W64-NEXT:    ; implicit-def: $vgpr0
-; GFX10W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
-; GFX10W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX10W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
+; GFX10W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX10W64-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX10W64-NEXT:  ; %bb.3:
-; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX10W64-NEXT:    s_load_dwordx4 s[8:11], s[2:3], 0x34
 ; GFX10W64-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX10W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W64-NEXT:    buffer_atomic_sub v0, v2, s[8:11], 0 idxen glc
 ; GFX10W64-NEXT:  .LBB7_4:
 ; GFX10W64-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX10W64-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W64-NEXT:    s_mov_b32 null, 0
 ; GFX10W64-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX10W64-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10W64-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
@@ -1886,37 +1936,38 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX10W32-LABEL: sub_i32_varying_vdata:
 ; GFX10W32:       ; %bb.0: ; %entry
-; GFX10W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX10W32-NEXT:    s_mov_b32 s2, 0
+; GFX10W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX10W32-NEXT:    s_mov_b32 s0, 0
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr1
 ; GFX10W32-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX10W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX10W32-NEXT:    s_ff1_i32_b32 s4, s3
+; GFX10W32-NEXT:    s_ff1_i32_b32 s4, s1
 ; GFX10W32-NEXT:    v_readlane_b32 s5, v0, s4
 ; GFX10W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX10W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX10W32-NEXT:    s_andn2_b32 s3, s3, s6
-; GFX10W32-NEXT:    s_add_i32 s2, s2, s5
-; GFX10W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX10W32-NEXT:    v_writelane_b32 v1, s0, s4
+; GFX10W32-NEXT:    s_andn2_b32 s1, s1, s6
+; GFX10W32-NEXT:    s_add_i32 s0, s0, s5
+; GFX10W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX10W32-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX10W32-NEXT:  ; %bb.2: ; %ComputeEnd
 ; GFX10W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX10W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX10W32-NEXT:    ; implicit-def: $vgpr0
-; GFX10W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX10W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX10W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX10W32-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX10W32-NEXT:  ; %bb.3:
-; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10W32-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10W32-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10W32-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX10W32-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10W32-NEXT:    buffer_atomic_sub v0, v2, s[4:7], 0 idxen glc
 ; GFX10W32-NEXT:  .LBB7_4:
 ; GFX10W32-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX10W32-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX10W32-NEXT:    s_mov_b32 null, 0
 ; GFX10W32-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX10W32-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10W32-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
@@ -1926,180 +1977,186 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
 ;
 ; GFX11W64-LABEL: sub_i32_varying_vdata:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX11W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX11W64-NEXT:    s_mov_b32 s4, 0
-; GFX11W64-NEXT:    ; implicit-def: $vgpr1
+; GFX11W64-NEXT:    ; implicit-def: $vgpr0
 ; GFX11W64-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX11W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11W64-NEXT:    s_ctz_i32_b64 s5, s[2:3]
-; GFX11W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11W64-NEXT:    v_readlane_b32 s8, v0, s5
+; GFX11W64-NEXT:    s_ctz_i32_b64 s5, s[0:1]
+; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11W64-NEXT:    v_readlane_b32 s8, v1, s5
 ; GFX11W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
-; GFX11W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX11W64-NEXT:    s_and_not1_b64 s[2:3], s[2:3], s[6:7]
+; GFX11W64-NEXT:    v_writelane_b32 v0, s4, s5
+; GFX11W64-NEXT:    s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
 ; GFX11W64-NEXT:    s_add_i32 s4, s4, s8
-; GFX11W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX11W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX11W64-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX11W64-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX11W64-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX11W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX11W64-NEXT:    ; implicit-def: $vgpr0
-; GFX11W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX11W64-NEXT:    v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX11W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX11W64-NEXT:    ; implicit-def: $vgpr1
+; GFX11W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX11W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX11W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX11W64-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX11W64-NEXT:  ; %bb.3:
-; GFX11W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, s4
+; GFX11W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W64-NEXT:    buffer_atomic_sub_u32 v0, v2, s[8:11], 0 idxen glc
+; GFX11W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], 0 idxen glc
 ; GFX11W64-NEXT:  .LBB7_4:
-; GFX11W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
-; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W64-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11W64-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
+; GFX11W64-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W64-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11W64-NEXT:    s_nop 0
 ; GFX11W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W64-NEXT:    s_endpgm
 ;
 ; GFX11W32-LABEL: sub_i32_varying_vdata:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX11W32-NEXT:    s_mov_b32 s2, 0
-; GFX11W32-NEXT:    ; implicit-def: $vgpr1
+; GFX11W32-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11W32-NEXT:    s_mov_b32 s0, 0
+; GFX11W32-NEXT:    ; implicit-def: $vgpr0
 ; GFX11W32-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX11W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11W32-NEXT:    s_ctz_i32_b32 s4, s3
-; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11W32-NEXT:    v_readlane_b32 s5, v0, s4
+; GFX11W32-NEXT:    s_ctz_i32_b32 s4, s1
+; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11W32-NEXT:    v_readlane_b32 s5, v1, s4
 ; GFX11W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX11W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX11W32-NEXT:    s_and_not1_b32 s3, s3, s6
-; GFX11W32-NEXT:    s_add_i32 s2, s2, s5
-; GFX11W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX11W32-NEXT:    v_writelane_b32 v0, s0, s4
+; GFX11W32-NEXT:    s_and_not1_b32 s1, s1, s6
+; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11W32-NEXT:    s_add_i32 s0, s0, s5
+; GFX11W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX11W32-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX11W32-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX11W32-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11W32-NEXT:    ; implicit-def: $vgpr0
-; GFX11W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX11W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX11W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11W32-NEXT:    ; implicit-def: $vgpr1
+; GFX11W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX11W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX11W32-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX11W32-NEXT:  ; %bb.3:
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11W32-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    buffer_atomic_sub_u32 v0, v2, s[4:7], 0 idxen glc
+; GFX11W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[4:7], 0 idxen glc
 ; GFX11W32-NEXT:  .LBB7_4:
-; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
-; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W32-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX11W32-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11W32-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
+; GFX11W32-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W32-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11W32-NEXT:    s_nop 0
 ; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11W32-NEXT:    s_endpgm
 ;
 ; GFX12W64-LABEL: sub_i32_varying_vdata:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_mov_b64 s[2:3], exec
+; GFX12W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX12W64-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX12W64-NEXT:    s_mov_b32 s4, 0
-; GFX12W64-NEXT:    ; implicit-def: $vgpr1
+; GFX12W64-NEXT:    ; implicit-def: $vgpr0
 ; GFX12W64-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX12W64-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX12W64-NEXT:    s_ctz_i32_b64 s5, s[2:3]
-; GFX12W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12W64-NEXT:    v_readlane_b32 s8, v0, s5
+; GFX12W64-NEXT:    s_ctz_i32_b64 s5, s[0:1]
+; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12W64-NEXT:    v_readlane_b32 s8, v1, s5
 ; GFX12W64-NEXT:    s_lshl_b64 s[6:7], 1, s5
-; GFX12W64-NEXT:    v_writelane_b32 v1, s4, s5
-; GFX12W64-NEXT:    s_and_not1_b64 s[2:3], s[2:3], s[6:7]
+; GFX12W64-NEXT:    v_writelane_b32 v0, s4, s5
+; GFX12W64-NEXT:    s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
 ; GFX12W64-NEXT:    s_add_co_i32 s4, s4, s8
-; GFX12W64-NEXT:    s_cmp_lg_u64 s[2:3], 0
+; GFX12W64-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; GFX12W64-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX12W64-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX12W64-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12W64-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX12W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX12W64-NEXT:    ; implicit-def: $vgpr0
-; GFX12W64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX12W64-NEXT:    v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX12W64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX12W64-NEXT:    ; implicit-def: $vgpr1
+; GFX12W64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX12W64-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12W64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
+; GFX12W64-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
 ; GFX12W64-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX12W64-NEXT:  ; %bb.3:
-; GFX12W64-NEXT:    s_load_b128 s[8:11], s[0:1], 0x34
+; GFX12W64-NEXT:    s_load_b128 s[8:11], s[2:3], 0x34
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12W64-NEXT:    v_mov_b32_e32 v0, s4
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
-; GFX12W64-NEXT:    buffer_atomic_sub_u32 v0, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX12W64-NEXT:    buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:  .LBB7_4:
-; GFX12W64-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W64-NEXT:    s_or_b64 exec, exec, s[0:1]
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
-; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W64-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX12W64-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12W64-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
+; GFX12W64-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
-; GFX12W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W64-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12W64-NEXT:    s_nop 0
 ; GFX12W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W64-NEXT:    s_endpgm
 ;
 ; GFX12W32-LABEL: sub_i32_varying_vdata:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12W32-NEXT:    s_mov_b32 s2, 0
-; GFX12W32-NEXT:    ; implicit-def: $vgpr1
+; GFX12W32-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX12W32-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12W32-NEXT:    s_mov_b32 s0, 0
+; GFX12W32-NEXT:    ; implicit-def: $vgpr0
 ; GFX12W32-NEXT:  .LBB7_1: ; %ComputeLoop
 ; GFX12W32-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT:    s_ctz_i32_b32 s4, s3
-; GFX12W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12W32-NEXT:    v_readlane_b32 s5, v0, s4
+; GFX12W32-NEXT:    s_ctz_i32_b32 s4, s1
+; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12W32-NEXT:    v_readlane_b32 s5, v1, s4
 ; GFX12W32-NEXT:    s_lshl_b32 s6, 1, s4
-; GFX12W32-NEXT:    v_writelane_b32 v1, s2, s4
-; GFX12W32-NEXT:    s_and_not1_b32 s3, s3, s6
-; GFX12W32-NEXT:    s_add_co_i32 s2, s2, s5
-; GFX12W32-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX12W32-NEXT:    v_writelane_b32 v0, s0, s4
+; GFX12W32-NEXT:    s_and_not1_b32 s1, s1, s6
+; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12W32-NEXT:    s_add_co_i32 s0, s0, s5
+; GFX12W32-NEXT:    s_cmp_lg_u32 s1, 0
 ; GFX12W32-NEXT:    s_cbranch_scc1 .LBB7_1
 ; GFX12W32-NEXT:  ; %bb.2: ; %ComputeEnd
-; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX12W32-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX12W32-NEXT:    ; implicit-def: $vgpr0
-; GFX12W32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
-; GFX12W32-NEXT:    s_xor_b32 s3, exec_lo, s3
+; GFX12W32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX12W32-NEXT:    ; implicit-def: $vgpr1
+; GFX12W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX12W32-NEXT:    s_xor_b32 s1, exec_lo, s1
 ; GFX12W32-NEXT:    s_cbranch_execz .LBB7_4
 ; GFX12W32-NEXT:  ; %bb.3:
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12W32-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    buffer_atomic_sub_u32 v0, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W32-NEXT:    buffer_atomic_sub_u32 v1, v2, s[4:7], null idxen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:  .LBB7_4:
-; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12W32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
-; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX12W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W32-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX12W32-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX12W32-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12W32-NEXT:    v_sub_nc_u32_e32 v1, s2, v1
+; GFX12W32-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
-; GFX12W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W32-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX12W32-NEXT:    s_nop 0
 ; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX12W32-NEXT:    s_endpgm
@@ -2113,8 +2170,8 @@ entry:
 define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
 ; GFX6-LABEL: sub_i32_varying_vindex:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_sub v1, v0, s[4:7], 0 idxen glc
@@ -2126,9 +2183,9 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX8-LABEL: sub_i32_varying_vindex:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_sub v2, v0, s[4:7], 0 idxen glc
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
@@ -2139,9 +2196,9 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX9-LABEL: sub_i32_varying_vindex:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_sub v1, v0, s[4:7], 0 idxen glc
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
@@ -2151,9 +2208,10 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ;
 ; GFX10-LABEL: sub_i32_varying_vindex:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 1
-; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    buffer_atomic_sub v1, v0, s[4:7], 0 idxen glc
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
@@ -2161,33 +2219,67 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: sub_i32_varying_vindex:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v1, 1
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], 0 idxen glc
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT:    s_nop 0
-; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: sub_i32_varying_vindex:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12-NEXT:    v_mov_b32_e32 v1, 1
-; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT:    s_nop 0
-; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX12-NEXT:    s_endpgm
+; GFX11W64-LABEL: sub_i32_varying_vindex:
+; GFX11W64:       ; %bb.0: ; %entry
+; GFX11W64-NEXT:    s_clause 0x1
+; GFX11W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX11W64-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11W64-NEXT:    v_mov_b32_e32 v1, 1
+; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11W64-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], 0 idxen glc
+; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W64-NEXT:    s_waitcnt vmcnt(0)
+; GFX11W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W64-NEXT:    s_nop 0
+; GFX11W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11W64-NEXT:    s_endpgm
+;
+; GFX11W32-LABEL: sub_i32_varying_vindex:
+; GFX11W32:       ; %bb.0: ; %entry
+; GFX11W32-NEXT:    s_clause 0x1
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX11W32-NEXT:    v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11W32-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], 0 idxen glc
+; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11W32-NEXT:    s_waitcnt vmcnt(0)
+; GFX11W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11W32-NEXT:    s_nop 0
+; GFX11W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11W32-NEXT:    s_endpgm
+;
+; GFX12W64-LABEL: sub_i32_varying_vindex:
+; GFX12W64:       ; %bb.0: ; %entry
+; GFX12W64-NEXT:    s_clause 0x1
+; GFX12W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W64-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12W64-NEXT:    v_mov_b32_e32 v1, 1
+; GFX12W64-NEXT:    s_wait_kmcnt 0x0
+; GFX12W64-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W64-NEXT:    s_wait_loadcnt 0x0
+; GFX12W64-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W64-NEXT:    s_nop 0
+; GFX12W64-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12W64-NEXT:    s_endpgm
+;
+; GFX12W32-LABEL: sub_i32_varying_vindex:
+; GFX12W32:       ; %bb.0: ; %entry
+; GFX12W32-NEXT:    s_clause 0x1
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W32-NEXT:    v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12W32-NEXT:    s_wait_kmcnt 0x0
+; GFX12W32-NEXT:    buffer_atomic_sub_u32 v1, v0, s[4:7], null idxen th:TH_ATOMIC_RETURN
+; GFX12W32-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12W32-NEXT:    s_wait_loadcnt 0x0
+; GFX12W32-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12W32-NEXT:    s_nop 0
+; GFX12W32-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12W32-NEXT:    s_endpgm
 entry:
   %lane = call i32 @llvm.amdgcn.workitem.id.x()
   %old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0, i32 0)
@@ -2199,10 +2291,10 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ; GFX6-LABEL: sub_i32_varying_offset:
 ; GFX6:       ; %bb.0: ; %entry
 ; GFX6-NEXT:    v_mov_b32_e32 v1, v0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s2, 0
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0xd
+; GFX6-NEXT:    s_mov_b32 s8, 0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_atomic_sub v2, v[0:1], s[4:7], 0 idxen offen glc
@@ -2214,15 +2306,14 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX8-LABEL: sub_i32_varying_offset:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s2, 0
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX8-NEXT:    s_mov_b32 s0, 0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, v0
-; GFX8-NEXT:    v_mov_b32_e32 v0, s2
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    buffer_atomic_sub v2, v[0:1], s[4:7], 0 idxen offen glc
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
@@ -2231,27 +2322,27 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX9-LABEL: sub_i32_varying_offset:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    s_mov_b32 s2, 0
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX9-NEXT:    s_mov_b32 s0, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v0
-; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_atomic_sub v2, v[0:1], s[4:7], 0 idxen offen glc
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_dword v0, v2, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: sub_i32_varying_offset:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX10-NEXT:    s_mov_b32 s2, 0
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x34
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 1
-; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    buffer_atomic_sub v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
@@ -2261,12 +2352,12 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX11W64-LABEL: sub_i32_varying_offset:
 ; GFX11W64:       ; %bb.0: ; %entry
-; GFX11W64-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W64-NEXT:    s_mov_b32 s2, 0
-; GFX11W64-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11W64-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W64-NEXT:    s_mov_b32 s0, 0
+; GFX11W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11W64-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W64-NEXT:    v_mov_b32_e32 v2, 1
-; GFX11W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX11W64-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W64-NEXT:    buffer_atomic_sub_u32 v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX11W64-NEXT:    v_mov_b32_e32 v0, 0
@@ -2278,12 +2369,12 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX11W32-LABEL: sub_i32_varying_offset:
 ; GFX11W32:       ; %bb.0: ; %entry
-; GFX11W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX11W32-NEXT:    s_mov_b32 s2, 0
+; GFX11W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX11W32-NEXT:    s_mov_b32 s0, 0
 ; GFX11W32-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11W32-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s2
+; GFX11W32-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_and_b32 v1, 0x3ff, v0
 ; GFX11W32-NEXT:    v_mov_b32_e32 v2, 1
-; GFX11W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
 ; GFX11W32-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11W32-NEXT:    buffer_atomic_sub_u32 v2, v[0:1], s[4:7], 0 idxen offen glc
 ; GFX11W32-NEXT:    v_mov_b32_e32 v0, 0
@@ -2295,11 +2386,12 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX12W64-LABEL: sub_i32_varying_offset:
 ; GFX12W64:       ; %bb.0: ; %entry
-; GFX12W64-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W64-NEXT:    v_mov_b32_e32 v1, v0
+; GFX12W64-NEXT:    s_clause 0x1
+; GFX12W64-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W64-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W64-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
 ; GFX12W64-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX12W64-NEXT:    v_mov_b32_e32 v2, 1
-; GFX12W64-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX12W64-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W64-NEXT:    buffer_atomic_sub_u32 v2, v[0:1], s[4:7], null idxen offen th:TH_ATOMIC_RETURN
 ; GFX12W64-NEXT:    s_wait_loadcnt 0x0
@@ -2310,10 +2402,11 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
 ;
 ; GFX12W32-LABEL: sub_i32_varying_offset:
 ; GFX12W32:       ; %bb.0: ; %entry
-; GFX12W32-NEXT:    s_load_b128 s[4:7], s[0:1], 0x34
-; GFX12W32-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, 0
+; GFX12W32-NEXT:    s_clause 0x1
+; GFX12W32-NEXT:    s_load_b128 s[4:7], s[2:3], 0x34
+; GFX12W32-NEXT:    s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12W32-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, 0x3ff, v0
 ; GFX12W32-NEXT:    v_mov_b32_e32 v2, 1
-; GFX12W32-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX12W32-NEXT:    s_wait_kmcnt 0x0
 ; GFX12W32-NEXT:    buffer_atomic_sub_u32 v2, v[0:1], s[4:7], null idxen offen th:TH_ATOMIC_RETURN
 ; GFX12W32-NEXT:    s_wait_loadcnt 0x0
@@ -2327,3 +2420,6 @@ entry:
   store i32 %old, ptr addrspace(1) %out
   ret void
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
author	Matt Arsenault <Matthew.Arsenault@amd.com>	2024-07-15 09:59:07 +0400
committer	Matt Arsenault <arsenm2@gmail.com>	2024-07-15 11:51:44 +0400
commit	b1bcb7ca460fcd317bbc8309e14c8761bf8394e0 (patch)
tree	cf2636217534435b2de9783a7cf8e9325819e658 /llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
parent	71051deff27928cff908ea794e09806eee662801 (diff)