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| author | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2014-09-23 08:48:01 +0000 |
|---|---|---|
| committer | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2014-09-23 08:48:01 +0000 |
| commit | 946b3b2e16357ea14b1efbf77f7b003f58766572 (patch) | |
| tree | 42be8ca8b13372192181612b462b9b969b6bc842 /llvm/test/Bitcode/terminatorInstructions.3.2.ll | |
| parent | 27720765ed1a12d7b998afb390d37c69b2c25aec (diff) | |
Ensure bitcode encoding stays stable.
This includes constants, attributes, and some additional instructions not covered by previous tests.
Work was done by lama.saba@intel.com.
llvm-svn: 218297
Diffstat (limited to 'llvm/test/Bitcode/terminatorInstructions.3.2.ll')
| -rw-r--r-- | llvm/test/Bitcode/terminatorInstructions.3.2.ll | 42 |
1 files changed, 35 insertions, 7 deletions
diff --git a/llvm/test/Bitcode/terminatorInstructions.3.2.ll b/llvm/test/Bitcode/terminatorInstructions.3.2.ll index 1bdbdcc4c98a..ba0f5ade2cc1 100644 --- a/llvm/test/Bitcode/terminatorInstructions.3.2.ll +++ b/llvm/test/Bitcode/terminatorInstructions.3.2.ll @@ -1,5 +1,4 @@ -; RUN: llvm-dis < %s.bc| FileCheck %s -; RUN: verify-uselistorder < %s.bc +; RUN: llvm-dis < %s.bc| FileCheck %s ; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. ; The test checks that LLVM does not misread terminator instructions from @@ -9,10 +8,10 @@ define i32 @condbr(i1 %cond){ entry: ; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel br i1 %cond, label %TrueLabel, label %FalseLabel - + TrueLabel: ret i32 1 - + FalseLabel: ret i32 0 } @@ -21,7 +20,7 @@ define i32 @uncondbr(){ entry: ; CHECK: br label %uncondLabel br label %uncondLabel - + uncondLabel: ret i32 1 } @@ -30,10 +29,10 @@ define i32 @indirectbr(i8* %Addr){ entry: ; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2] indirectbr i8* %Addr, [ label %bb1, label %bb2 ] - + bb1: ret i32 1 - + bb2: ret i32 0 } @@ -42,7 +41,36 @@ define void @unreachable(){ entry: ; CHECK: unreachable unreachable + + ret void +} + +define i32 @retInstr(){ +entry: +; CHECK: ret i32 1 + ret i32 1 +} +define void @retInstr2(){ +entry: +; CHECK: ret void ret void } +define i32 @switchInstr(i32 %x){ +entry: +; CHECK: switch i32 %x, label %label3 [ + switch i32 %x, label %label3 [ +; CHECK-NEXT: i32 1, label %label1 + i32 1, label %label1 +; CHECK-NEXT: i32 2, label %label2 + i32 2, label %label2 + ] +label1: + ret i32 1 +label2: + ret i32 2 +label3: + ret i32 0 +} + |