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| author | CarolineConcatto <caroline.concatto@arm.com> | 2024-10-28 16:36:02 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-28 16:36:02 +0000 |
| commit | 106259510f6a7a3824dd34f78a77ead150dd2154 (patch) | |
| tree | 5794f78f487efe0fbe2b31e647f0c53d229e5d65 /llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp | |
| parent | 7a710110fcb2ad5d903ec41ba6a63193cf03edc0 (diff) | |
[AArch64]Add convert and multiply-add SIMD&FP assembly/disassembly in… (#113296)
…structions
This patch adds the following instructions:
Conversion between floating-point and integer:
FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU}
{S,U}CVTF
Advanced SIMD three-register extension:
FMMLA
According to https://developer.arm.com/documentation/ddi0602
Co-authored-by: Marian Lukac marian.lukac@arm.com
Co-authored-by: Spencer Abson spencer.abson@arm.com
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp')
0 files changed, 0 insertions, 0 deletions