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| author | Fanchen Kong <fanchen.kong@intel.com> | 2022-09-21 21:05:44 -0700 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2022-09-21 21:05:44 -0700 |
| commit | 8a2729fea719c7ef1353135a0e9cb5866d5178b7 (patch) | |
| tree | 18fa0c05bff46bfa86c3b8c00e662febd6402076 /llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | |
| parent | 6782d71680ea1cbddd7a98f176e2d9b5b78536d8 (diff) | |
[WebAssembly] Improve codegen for loading scalars from memory to v128
Use load32_zero instead of load32_splat to load the low 32 bits from memory to
v128. Test cases are added to cover this change.
Reviewed By: tlively
Differential Revision: https://reviews.llvm.org/D134257
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 36393aea293c..995fb1d74ce5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -285,14 +285,16 @@ defm "" : SIMDLoadZero<I32x4, 0x5c>; defm "" : SIMDLoadZero<I64x2, 0x5d>; // Use load_zero to load scalars into vectors as well where possible. -// TODO: i32, i16, and i8 scalars -def load_scalar : - PatFrag<(ops node:$addr), (scalar_to_vector (i64 (load $addr)))>; -defm : LoadPatNoOffset<v2i64, load_scalar, "LOAD_ZERO_I64x2">; -defm : LoadPatImmOff<v2i64, load_scalar, regPlusImm, "LOAD_ZERO_I64x2">; -defm : LoadPatImmOff<v2i64, load_scalar, or_is_add, "LOAD_ZERO_I64x2">; -defm : LoadPatOffsetOnly<v2i64, load_scalar, "LOAD_ZERO_I64x2">; -defm : LoadPatGlobalAddrOffOnly<v2i64, load_scalar, "LOAD_ZERO_I64x2">; +// TODO: i16, and i8 scalars +foreach vec = [I32x4, I64x2] in { + defvar inst = "LOAD_ZERO_"#vec; + defvar pat = PatFrag<(ops node:$addr), (scalar_to_vector (vec.lane_vt (load $addr)))>; + defm : LoadPatNoOffset<vec.vt, pat, inst>; + defm : LoadPatImmOff<vec.vt, pat, regPlusImm, inst>; + defm : LoadPatImmOff<vec.vt, pat, or_is_add, inst>; + defm : LoadPatOffsetOnly<vec.vt, pat, inst>; + defm : LoadPatGlobalAddrOffOnly<vec.vt, pat, inst>; +} // TODO: f32x4 and f64x2 as well foreach vec = [I32x4, I64x2] in { |