diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
| commit | e3a676e9adba668a7da944766218e98dd4b2c10a (patch) | |
| tree | 632a983ae9fe72b635cf72262bf2e9a0cbe6dce3 /llvm/lib/Target/SystemZ/SystemZElimCompare.cpp | |
| parent | 3260ef16bbdecc391d7da8fe3bbe19585f6ccb19 (diff) | |
CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().
llvm-svn: 364191
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZElimCompare.cpp')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZElimCompare.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 4c13cd6bfca7..9cbf6b320504 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -525,9 +525,9 @@ bool SystemZElimCompare::fuseCompareOperations( // SrcReg2 is the register if the source operand is a register, // 0 if the source operand is immediate, and the base register // if the source operand is memory (index is not supported). - unsigned SrcReg = Compare.getOperand(0).getReg(); - unsigned SrcReg2 = - Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : 0; + Register SrcReg = Compare.getOperand(0).getReg(); + Register SrcReg2 = + Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register(); MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch; for (++MBBI; MBBI != MBBE; ++MBBI) if (MBBI->modifiesRegister(SrcReg, TRI) || |