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| author | Brox Chen <guochen2@amd.com> | 2025-04-27 14:30:34 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-27 14:30:34 -0400 |
| commit | 72bc0525d88c2df4a2c370ad8a11de8d0fdd52bf (patch) | |
| tree | bbae63f6461228ed439fa183d765ac7b186595de /llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | |
| parent | daa1e175531495b0ba07179a2c7fc609eb7d371c (diff) | |
[AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)
We currently just need to shift down 32bit wwm registers.
Previous check condition mistakenly select 16bit registers in true16
mode. Update check condition to skip the 16bit register in wmm reg
sorting
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 0c1cd9ceddb0..e29aeb84f766 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1650,7 +1650,7 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, // are of 32-bit size. SIPreAllocateWWMRegs pass can add tuples into WWM // reserved registers. const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); - if (TRI->getRegSizeInBits(*RC) > 32) + if (TRI->getRegSizeInBits(*RC) != 32) continue; SortedWWMVGPRs.push_back(Reg); } |