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authorPravin Jagtap <Pravin.Jagtap@amd.com>2024-09-24 14:41:45 +0530
committerGitHub <noreply@github.com>2024-09-24 14:41:45 +0530
commit3659aa8079e00d7bd4f2d9c68c404a93ec297200 (patch)
treef6a2a28516e09eb0849a14b318f665473d245a1a /llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
parentc5672e21ca2a16ff18cdaa83db11d2edb84c5e14 (diff)
[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
Both SGPR->VGPR and VGPR->AGPR spilling code give a fixup to the spill frame indices referred in debug instructions so that they can be entirely removed. The stack argument is present at 0th index in DBG_VALUE and at 2nd index for DBG_VALUE_LIST. Fixes: SWDEV-484156
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFrameLowering.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIFrameLowering.cpp13
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 2c67c4aedfe4..50a6f028f66d 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1418,10 +1418,15 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
// the debug value instructions. We should instead, update it with the
// correct register value. But not sure the register value alone is
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
- !MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
- SpillFIs[MI.getOperand(0).getIndex()]) {
- MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
+ if (MI.isDebugValue()) {
+ uint32_t StackOperandIdx = MI.isDebugValueList() ? 2 : 0;
+ if (MI.getOperand(StackOperandIdx).isFI() &&
+ !MFI.isFixedObjectIndex(
+ MI.getOperand(StackOperandIdx).getIndex()) &&
+ SpillFIs[MI.getOperand(StackOperandIdx).getIndex()]) {
+ MI.getOperand(StackOperandIdx)
+ .ChangeToRegister(Register(), false /*isDef*/);
+ }
}
}
}