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| author | Brox Chen <guochen2@amd.com> | 2024-11-20 11:33:04 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-20 11:33:04 -0500 |
| commit | 9fb01fcd9fd5ccffa2421096e5e058156b86aa84 (patch) | |
| tree | ed19c42653c067d726c868617774892f0a12849e /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 934140a3353f6d480a01a1f68d42899c926ee056 (diff) | |
[AMDGPU][MC][True16] Support VOP2 instructions with true16 format (#115233)
Support true16 format for VOP2 instructions in MC
This patch updates the true16 and fake16 vop_profile for the following
instructions and update the asm/dasm tests:
v_fmac_f16
v_fmamk_f16
v_fmaak_f16
It seems vop2_t16_promote.s files are not yet updated with true16 flag
in the previous batch update. It will be updated seperately
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 7c293c1a5e51..06df08feda8f 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -347,6 +347,25 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics> +static DecodeStatus +decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm, + uint64_t /*Addr*/, + const MCDisassembler *Decoder) { + const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); + assert(isUInt<9>(Imm) && "9-bit encoding expected"); + + if (Imm & AMDGPU::EncValues::IS_VGPR) { + bool IsHi = Imm & (1 << 7); + unsigned RegIdx = Imm & 0x7f; + return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); + } + return addOperand(Inst, DAsm->decodeNonVGPRSrcOp( + OpWidth, Imm & 0xFF, true, ImmWidth, + (AMDGPU::OperandSemantics)OperandSemantics)); +} + +template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, + unsigned OperandSemantics> static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, const MCDisassembler *Decoder) { |