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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-25 19:51:01 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-25 19:51:01 -0800 |
| commit | 716364ebd6649aeca8658680ebb8b0424d028006 (patch) | |
| tree | 70bf3822d98f15c408dab87d2d7cc96b219b09a6 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | aa7eb5723cb4499f35ed1c5455f668ccc078e7c2 (diff) | |
AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)
The encoding of v_dot2c_f32_bf16 opcode is same as v_mac_f32 in gfx90a,
both from gfx9 series. This required a new decoderNameSpace GFX950_DOT.
Co-authored-by: Sirish Pande <Sirish.Pande@amd.com>
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 983a10027b20..590835180572 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -566,6 +566,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS)) break; + if (STI.hasFeature(AMDGPU::FeatureGFX950Insts) && + tryDecodeInst(DecoderTableGFX95064, MI, QW, Address, CS)) + break; + // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and // v_mad_mixhi_f16 for FMA variants. Try to decode using this special // table first so we print the correct name. @@ -627,6 +631,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (isGFX9() && tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS)) break; + if (STI.hasFeature(AMDGPU::FeatureGFX950Insts) && + tryDecodeInst(DecoderTableGFX95032, MI, DW, Address, CS)) + break; + if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS)) break; |