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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-25 19:27:01 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-25 19:27:01 -0800 |
| commit | 22503a9df16e8bf320c81ffbd3b4c70de45f8053 (patch) | |
| tree | 62353a5ac16dca072adc4c5f61352df16063dac0 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 658db918fe47efc0a3ba0556d58d607f0919f1e3 (diff) | |
AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index fa5f86b0788c..983a10027b20 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -262,6 +262,7 @@ DECODE_OPERAND_REG_8(VGPR_32_Lo128) DECODE_OPERAND_REG_8(VReg_64) DECODE_OPERAND_REG_8(VReg_96) DECODE_OPERAND_REG_8(VReg_128) +DECODE_OPERAND_REG_8(VReg_192) DECODE_OPERAND_REG_8(VReg_256) DECODE_OPERAND_REG_8(VReg_288) DECODE_OPERAND_REG_8(VReg_352) |