Revert "[AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (#114500)"

This reverts commit f7a5f067885b7f6cc4a000c8392adf6b777a9108.

Fails to build with:

llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp:126:37: error: no member named 'OPERAND_LAST' in 'llvm::AMDGPU::OpName'
  126 |   uint16_t OpName = AMDGPU::OpName::OPERAND_LAST;

1 files changed, 1 insertions, 58 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 5408e72528c7..38272b9d4840 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -114,63 +114,9 @@ bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
   llvm_unreachable("unknown operand type");
 }
 
-// Lower true16 D16 Pseudo instruction to d16_lo/d16_hi MCInst based on
-// Dst/Data's .l/.h selection
-void AMDGPUMCInstLower::lowerT16D16Helper(const MachineInstr *MI,
-                                          MCInst &OutMI) const {
-  unsigned Opcode = MI->getOpcode();
-  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
-  const SIRegisterInfo &TRI = TII->getRegisterInfo();
-  const auto *Info = AMDGPU::getT16D16Helper(Opcode);
-
-  uint16_t OpName = AMDGPU::OpName::OPERAND_LAST;
-  if (TII->isDS(Opcode)) {
-    if (MI->mayLoad())
-      OpName = llvm::AMDGPU::OpName::vdst;
-    else if (MI->mayStore())
-      OpName = llvm::AMDGPU::OpName::data0;
-    else
-      llvm_unreachable("LDS load or store expected");
-  } else {
-    OpName = AMDGPU::hasNamedOperand(Opcode, llvm::AMDGPU::OpName::vdata)
-                 ? llvm::AMDGPU::OpName::vdata
-                 : llvm::AMDGPU::OpName::vdst;
-  }
-
-  // select Dst/Data
-  int VDstOrVDataIdx = AMDGPU::getNamedOperandIdx(Opcode, OpName);
-  const MachineOperand &MIVDstOrVData = MI->getOperand(VDstOrVDataIdx);
-
-  // select hi/lo MCInst
-  bool IsHi = AMDGPU::isHi16Reg(MIVDstOrVData.getReg(), TRI);
-  Opcode = IsHi ? Info->HiOp : Info->LoOp;
-
-  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
-  assert(MCOpcode != -1 &&
-         "Pseudo instruction doesn't have a target-specific version");
-  OutMI.setOpcode(MCOpcode);
-
-  // lower operands
-  for (int I = 0, E = MI->getNumExplicitOperands(); I < E; I++) {
-    const MachineOperand &MO = MI->getOperand(I);
-    MCOperand MCOp;
-    if (I == VDstOrVDataIdx)
-      MCOp = MCOperand::createReg(TRI.get32BitRegister(MIVDstOrVData.getReg()));
-    else
-      lowerOperand(MO, MCOp);
-    OutMI.addOperand(MCOp);
-  }
-
-  if (AMDGPU::hasNamedOperand(MCOpcode, AMDGPU::OpName::vdst_in)) {
-    MCOperand MCOp;
-    lowerOperand(MIVDstOrVData, MCOp);
-    OutMI.addOperand(MCOp);
-  }
-}
-
 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
   unsigned Opcode = MI->getOpcode();
-  const auto *TII = static_cast<const SIInstrInfo *>(ST.getInstrInfo());
+  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
 
   // FIXME: Should be able to handle this with lowerPseudoInstExpansion. We
   // need to select it to the subtarget specific version, and there's no way to
@@ -191,9 +137,6 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
              Opcode == AMDGPU::SI_TCRETURN_GFX) {
     // TODO: How to use branch immediate and avoid register+add?
     Opcode = AMDGPU::S_SETPC_B64;
-  } else if (AMDGPU::getT16D16Helper(Opcode)) {
-    lowerT16D16Helper(MI, OutMI);
-    return;
   }
 
   int MCOpcode = TII->pseudoToMCOpcode(Opcode);