diff options
| author | Craig Topper <craig.topper@sifive.com> | 2025-03-02 22:56:56 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2025-03-02 23:46:18 -0800 |
| commit | 7cee4c7c59fdbb28fb7b502ea39da521b1e634a2 (patch) | |
| tree | 9fcb23c0de8406adb90f0f80676310c809f4bc5c /llvm/lib/CodeGen/CallingConvLower.cpp | |
| parent | 9f8e148a6cdcdb8e89c284c2bc71e3ea28d2c5f1 (diff) | |
[CallingConvLower] Use MCRegister. NFC
Diffstat (limited to 'llvm/lib/CodeGen/CallingConvLower.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/CallingConvLower.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/CallingConvLower.cpp b/llvm/lib/CodeGen/CallingConvLower.cpp index cebc9f5c4639..b71e7812296c 100644 --- a/llvm/lib/CodeGen/CallingConvLower.cpp +++ b/llvm/lib/CodeGen/CallingConvLower.cpp @@ -198,7 +198,7 @@ static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { return (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall); } -void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, +void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCRegister> &Regs, MVT VT, CCAssignFn Fn) { uint64_t SavedStackSize = StackSize; Align SavedMaxStackArgAlign = MaxStackArgAlign; @@ -227,7 +227,7 @@ void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, assert(NumLocs < Locs.size() && "CC assignment failed to add location"); for (unsigned I = NumLocs, E = Locs.size(); I != E; ++I) if (Locs[I].isRegLoc()) - Regs.push_back(MCPhysReg(Locs[I].getLocReg())); + Regs.push_back(Locs[I].getLocReg()); // Clear the assigned values and stack memory. We leave the registers marked // as allocated so that future queries don't return the same registers, i.e. @@ -247,11 +247,11 @@ void CCState::analyzeMustTailForwardedRegisters( SaveAndRestore SavedMustTail(AnalyzingMustTailForwardedRegs, true); for (MVT RegVT : RegParmTypes) { - SmallVector<MCPhysReg, 8> RemainingRegs; + SmallVector<MCRegister, 8> RemainingRegs; getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); const TargetLowering *TL = MF.getSubtarget().getTargetLowering(); const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); - for (MCPhysReg PReg : RemainingRegs) { + for (MCRegister PReg : RemainingRegs) { Register VReg = MF.addLiveIn(PReg, RC); Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); } |
