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| author | Craig Topper <craig.topper@intel.com> | 2020-04-27 11:53:41 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-04-27 12:00:24 -0700 |
| commit | bdbbed115f87fd2700bf10249c6a63625f59a809 (patch) | |
| tree | d9484e03796087112ac84ea0d6f90594c9b9d2a9 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4b9bef7e6cae4212ab7325ab3165ce01be4344bc (diff) | |
[X86][CostModel] Update costs for vector truncate with avx512f/avx512bw.
All avx512 truncate instructions except vXi64->vXi32 are 2 uops
on port 5. So raise their costs to 2. Except when we have an
earlier faster sequence like pshufb for 128 bit input vectors.
Add a lower cost of 3 v16i16->v16i8 with avx512f where we can
extend to v16i32 then truncate. And a cost of 2 for avx512bw with
and without avx512vl. There we can use vpmovwb with either a ymm
or zmm input. Both of these beat masking, splitting, and using
packuswb which is our avx/avx2 codegen.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions
