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| author | Dinar Temirbulatov <Dinar.Temirbulatov@arm.com> | 2024-07-19 10:18:52 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-19 10:18:52 +0100 |
| commit | b7b0071680e60c60da9d4d858f944fd95d76fd42 (patch) | |
| tree | 52566cec50367b048f5706b5cddddfd6a78560d2 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 6235698f47828747d3b1b0418e547e2e4ff9138f (diff) | |
[AArch64][SVE] Improve code quality of vector unsigned/signed add reductions. (#97339)
For SVE we don't have to zero extend and sum part of the result before
issuing UADDV instruction. Also this change allows to handle bigger than
a legal vector type more efficiently and lower a fixed-length vector
type to SVE's UADDV where appropriate.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions