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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-01-21 12:04:10 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2019-01-21 12:04:10 +0000 |
| commit | b68dd05c14fc232de9be2d88e4f5e2df9e83bd54 (patch) | |
| tree | 54d664074aea95bc8a43b75b113a7d5d21d69417 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 44feb4a87bcfc732e1d926dfa45fdd9b4289b2fe (diff) | |
[X86][BtVer2] Update the WriteLoad latency.
r327630 introduced new write definitions for float/vector loads.
Before that revision, WriteLoad was used by both integer/float (scalar/vector)
load. So, WriteLoad had to conservatively declare a latency to 5cy. That is
because the load-to-use latency for float/vector load is 5cy.
Now that we have dedicated writes for float/vector loads, there is no reason why
we should keep the latency of WriteLoad to 5cy. At the moment, WriteLoad is only
used by scalar integer loads only; we can assume an optimstic 3cy latency for
them.
This patch changes that latency from 5cy to 3cy, and regenerates the affected
scheduling/mca tests.
Differential Revision: https://reviews.llvm.org/D56922
llvm-svn: 351742
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions
