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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2024-11-06 14:53:42 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-06 14:53:42 -0800 |
| commit | 7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4 (patch) | |
| tree | 203cf9459a848fed7c7a16fde0b2b17545fecd49 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | a6637ae2cc9a0e7c9a37603b3d277d7ca642bc36 (diff) | |
[RISCV] Refine vector division latencies in SiFive P600's scheduling model (#115038)
For both vector integer and floating point divisions.
Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com>
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions