diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2022-06-10 10:58:39 -0700 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2022-06-13 13:23:33 -0700 |
| commit | cb9ae93712464858c8deaf18dea25d41a9d5212a (patch) | |
| tree | 0cb8e04487b79ed95d909adef772f2f3de9b0e80 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 7316b0d54c3d00d9142c881f0c3f400b664c30b4 (diff) | |
[AMDGPU] Define SGPR_NULL64 register. NFCI.
On gfx10+ null register can be used as both 32 and 64 bit operand.
Define a 64 bit version of the register to use during codegen.
Differential Revision: https://reviews.llvm.org/D127527
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions