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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-18 10:44:55 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-18 10:44:55 -0800 |
| commit | cab732861c4885b714c70f2945de9f1dd4d725fa (patch) | |
| tree | 1d364a11b12c571c48563e962d61a56a45feedd5 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | a6fc489bb7a2e9fb3a7f70cccc181e4ee70374bf (diff) | |
AMDGPU: Add subtarget features for minimum3/maximum3 instructions (#116308)
gfx12 and gfx950 managed to produce 3 different permutations of this feature.
gfx12 supports f32 and f16, and gfx950 supports f32 and v2f16.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions