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| author | Igor Breger <igor.breger@intel.com> | 2016-02-24 08:15:20 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-02-24 08:15:20 +0000 |
| commit | c7ba5699c5a9e908c05a2a94f56852300095a280 (patch) | |
| tree | 4634f6aea1ef12c8859cf4ecc0ec42deed01de0b /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 2c56f33dbf6d56f61ecdff2cc75a2c1a53f16584 (diff) | |
AVX512: Add vpmovzxbw/d/q ,vpmovzxw/d/q ,vpmovzxbdq lowering patterns that support 256bit inputs like AVX patterns ( that are disable in case HasVLX , see SS41I_pmovx_avx2_patterns).
Differential Revision: http://reviews.llvm.org/D17504
llvm-svn: 261724
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions