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authorCraig Topper <craig.topper@sifive.com>2021-03-26 14:15:27 -0700
committerCraig Topper <craig.topper@sifive.com>2021-03-26 14:15:29 -0700
commitc41f2f6492824b15c1fbf6a6f64f168b9c5621c0 (patch)
tree5954394cdce72f0765263e3715398c755298c073 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parentd50fe9f0d6b9ee61df8830a67ea0a33c27a637e7 (diff)
[RISCV] Add scheduler classes for the Zba and Zbb extensions.
I've used IALU for the simplest operations from Zbb: min, minu, max, maxu, sext.b, sext.h, zext.h, andn, orn, xnor I've put add.uw in IALU32 and slli.uw in ShiftImm32. Remaining instructions have received new classes. All 3 sh*add are grouped together. sh*add.uw are grouped together. Rotate left and right are together. Everything else got their own class containing one instruction. I think what I have here is the minimum granularity we need. I could be convinced that we need more classes. Reviewed By: evandro Differential Revision: https://reviews.llvm.org/D99040
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