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| author | Koakuma <koachan@protonmail.com> | 2025-05-04 09:39:08 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-04 09:39:08 +0700 |
| commit | c34d2fb59974dbad07a41987896dff7da8ec8a67 (patch) | |
| tree | 7bb4a114dcc9e41a585e861c9c5eb218e9ab78ec /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 56433e874b96bf7b3da02c13226a996d4fa5aef8 (diff) | |
[SPARC] Mark Niagara3 as VIS3-capable
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:
> T3 SPARC core has a new 9 stage floating point pipeline and added Fused
> Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
> UltraSPARC T2/T2+.
Reviewers: rorth, s-barannikov, brad0
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/138399
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions