diff options
| author | Adrian Tong <adriantong1024@gmail.com> | 2021-11-23 00:11:45 +0000 |
|---|---|---|
| committer | Adrian Tong <adriantong1024@gmail.com> | 2022-01-20 01:57:40 +0000 |
| commit | b6a7ae2c5ddc2ea47d0272f42c73672bc4a633cd (patch) | |
| tree | c513449b272f1fb7333f9eed83d76399540a4f61 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 02d9a4d56d7bfd353372ed8afaf2c1350d184145 (diff) | |
Optimize shift and accumulate pattern in AArch64.
AArch64 supports unsigned shift right and accumulate. In case we see a
unsigned shift right followed by an OR. We could turn them into a USRA
instruction, given the operands of the OR has no common bits.
Differential Revision: https://reviews.llvm.org/D114405
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions