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| author | Craig Topper <craig.topper@sifive.com> | 2021-10-28 15:09:09 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-10-29 09:49:36 -0700 |
| commit | aefcd598959abbea5eddf1fe454359f53bd9d853 (patch) | |
| tree | 054c7eae8a9836d572ee9092d8e269cefda9af35 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 1deccd05ba8a326e57a513002f482ed0924b1fd8 (diff) | |
[RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register instructions better.
If the VL operand of a mask register instruction comes from an
explicit vsetvli with a different VTYPE, we can still avoid needing
a vsetvli as long as the SEW/LMUL ratio is the same and policy bits
match.
Differential Revision: https://reviews.llvm.org/D112762
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions