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| author | Piyou Chen <piyou.chen@sifive.com> | 2023-11-16 22:34:31 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-16 22:34:31 +0800 |
| commit | ac4868ea3c495baf5cbcb729e03f95b4425420dc (patch) | |
| tree | d8e7bb662be1295001e962391a55467660597a3e /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | c0c8679f047e78fbf5d6baa3e9640a3d7e155620 (diff) | |
[RISCV] Split regalloc between RVV and other (#72096)
Enable this flow by -riscv-split-regalloc=1 (default disable), and could
designate specific allocator to RVV by
-riscv-rvv-regalloc=<fast|basic|greedy>
It uses the RegClass filter function to decide which regclass need to be
processed.
This patch is pre-requirement for supporting PostRA vsetvl insertion
pass.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions