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| author | XiangZhang <xiang.zhang@iluvatar.com> | 2025-07-02 11:08:58 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-02 11:08:58 +0800 |
| commit | aa1d9a4c31040daa7686560e24f7c06090f8a2e6 (patch) | |
| tree | 16bcd881405f71ab98042dccfac3987cee33da2c /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | eb07f0d4a933d18dbf9f606d533baced2a1a19ca (diff) | |
[MLIR][Affine] Enhance simplifyAdd for AffineExpr mod (#146492)
Currently AffineExpr Add has ability to optimize `"s1 + (s1 // c * -c)"
to "s1 % c"`,
but can not optimize `"(s0 + s1) + (s1 // c * -c)"`.
This patch provide an opportunity to do this simplification, let it can
be simplified to `"s0 + s1 % c"`.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions