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authorSanjay Patel <spatel@rotateright.com>2021-07-12 08:58:05 -0400
committerSanjay Patel <spatel@rotateright.com>2021-07-12 09:01:26 -0400
commita488c7879e688f40647f0deacd7e09ec3082e4a4 (patch)
tree1bea136bf4a298999864504fe4331b1abb79488a /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parent4b9d698243c4170e4ecf7f4336cd2824d2641e2a (diff)
[InstCombine] reduce signbit test of logic ops to cmp with zero
This is the pattern from the description of: https://llvm.org/PR50816 There might be a way to generalize this to a smaller or more generic pattern, but I have not found it yet. https://alive2.llvm.org/ce/z/ShzJoF define i1 @src(i8 %x) { %add = add i8 %x, -1 %xor = xor i8 %x, -1 %and = and i8 %add, %xor %r = icmp slt i8 %and, 0 ret i1 %r } define i1 @tgt(i8 %x) { %r = icmp eq i8 %x, 0 ret i1 %r }
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions