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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-11-28 15:16:23 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-28 15:16:23 +0800 |
| commit | 93f7398bdba9d1547df21156db4d5393f0ab5ec8 (patch) | |
| tree | 886b5be87d350d82d9b6ae35774f01bad389dfcc /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | c4645ffedacad18e4cd1dd372288aa55178b1c44 (diff) | |
[RISCV] Add TuneDisableLatencySchedHeuristic
This tune feature will disable latency scheduling heuristic.
This can reduce the number of spills/reloads but will cause some
regressions on some cores.
CPU may add this tune feature if they find it's profitable.
Reviewers: lukel97, michaelmaitland, asb, preames, mshockwave, topperc
Reviewed By: michaelmaitland, mshockwave, topperc
Pull Request: https://github.com/llvm/llvm-project/pull/115858
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions