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| author | Zakk Chen <zakk.chen@sifive.com> | 2021-03-15 07:22:12 -0700 |
|---|---|---|
| committer | Zakk Chen <zakk.chen@sifive.com> | 2021-03-26 07:23:24 -0700 |
| commit | 9049cf77e39443b479b5c8f56f88b93c698c7876 (patch) | |
| tree | 4a48ad3db815b5701ace6af83c3f79ac2982ca1b /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 6f91cf75d7f55c7beadeebeac7c1010a2e7c6553 (diff) | |
[RISCV] Add constraint for RVV indexed loads.
Add the constraint when destination EEW not equals the source EEW for
correctness.
The RVV spec has three register overlap rules and I implement the first
stricter constraint because the others are difficult to enforce.
Reviewed By: frasercrmck, craig.topper
Differential Revision: https://reviews.llvm.org/D98920
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions